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- STMicroelectronics STM32 Reset and Clock Controller
- ===================================================
- The RCC IP is both a reset and a clock controller.
- Please refer to clock-bindings.txt for common clock controller binding usage.
- Please also refer to reset.txt for common reset controller binding usage.
- Required properties:
- - compatible: Should be:
- "st,stm32f42xx-rcc"
- "st,stm32f469-rcc"
- - reg: should be register base and length as documented in the
- datasheet
- - #reset-cells: 1, see below
- - #clock-cells: 2, device nodes should specify the clock in their "clocks"
- property, containing a phandle to the clock device node, an index selecting
- between gated clocks and other clocks and an index specifying the clock to
- use.
- Example:
- rcc: rcc@40023800 {
- #reset-cells = <1>;
- #clock-cells = <2>
- compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
- reg = <0x40023800 0x400>;
- };
- Specifying gated clocks
- =======================
- The primary index must be set to 0.
- The secondary index is the bit number within the RCC register bank, starting
- from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
- It is calculated as: index = register_offset / 4 * 32 + bit_offset.
- Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
- To simplify the usage and to share bit definition with the reset and clock
- drivers of the RCC IP, macros are available to generate the index in
- human-readble format.
- For STM32F4 series, the macro are available here:
- - include/dt-bindings/mfd/stm32f4-rcc.h
- Example:
- /* Gated clock, AHB1 bit 0 (GPIOA) */
- ... {
- clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
- };
- /* Gated clock, AHB2 bit 4 (CRYP) */
- ... {
- clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
- };
- Specifying other clocks
- =======================
- The primary index must be set to 1.
- The secondary index is bound with the following magic numbers:
- 0 SYSTICK
- 1 FCLK
- Example:
- /* Misc clock, FCLK */
- ... {
- clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
- };
- Specifying softreset control of devices
- =======================================
- Device nodes should specify the reset channel required in their "resets"
- property, containing a phandle to the reset device node and an index specifying
- which channel to use.
- The index is the bit number within the RCC registers bank, starting from RCC
- base address.
- It is calculated as: index = register_offset / 4 * 32 + bit_offset.
- Where bit_offset is the bit offset within the register.
- For example, for CRC reset:
- crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
- example:
- timer2 {
- resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
- };
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