rockchip,rk3288-cru.txt 1.9 KB

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  1. * Rockchip RK3288 Clock and Reset Unit
  2. The RK3288 clock controller generates and supplies clock to various
  3. controllers within the SoC and also implements a reset controller for SoC
  4. peripherals.
  5. Required Properties:
  6. - compatible: should be "rockchip,rk3288-cru"
  7. - reg: physical base address of the controller and length of memory mapped
  8. region.
  9. - #clock-cells: should be 1.
  10. - #reset-cells: should be 1.
  11. Optional Properties:
  12. - rockchip,grf: phandle to the syscon managing the "general register files"
  13. If missing pll rates are not changable, due to the missing pll lock status.
  14. Each clock is assigned an identifier and client nodes can use this identifier
  15. to specify the clock which they consume. All available clocks are defined as
  16. preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
  17. used in device tree sources. Similar macros exist for the reset sources in
  18. these files.
  19. External clocks:
  20. There are several clocks that are generated outside the SoC. It is expected
  21. that they are defined using standard clock bindings with following
  22. clock-output-names:
  23. - "xin24m" - crystal input - required,
  24. - "xin32k" - rtc clock - optional,
  25. - "ext_i2s" - external I2S clock - optional,
  26. - "ext_hsadc" - external HSADC clock - optional,
  27. - "ext_edp_24m" - external display port clock - optional,
  28. - "ext_vip" - external VIP clock - optional,
  29. - "ext_isp" - external ISP clock - optional,
  30. - "ext_jtag" - external JTAG clock - optional
  31. Example: Clock controller node:
  32. cru: cru@20000000 {
  33. compatible = "rockchip,rk3188-cru";
  34. reg = <0x20000000 0x1000>;
  35. rockchip,grf = <&grf>;
  36. #clock-cells = <1>;
  37. #reset-cells = <1>;
  38. };
  39. Example: UART controller node that consumes the clock generated by the clock
  40. controller:
  41. uart0: serial@10124000 {
  42. compatible = "snps,dw-apb-uart";
  43. reg = <0x10124000 0x400>;
  44. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  45. reg-shift = <2>;
  46. reg-io-width = <1>;
  47. clocks = <&cru SCLK_UART0>;
  48. };