rockchip,rk3188-cru.txt 2.0 KB

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  1. * Rockchip RK3188/RK3066 Clock and Reset Unit
  2. The RK3188/RK3066 clock controller generates and supplies clock to various
  3. controllers within the SoC and also implements a reset controller for SoC
  4. peripherals.
  5. Required Properties:
  6. - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
  7. "rockchip,rk3066a-cru"
  8. - reg: physical base address of the controller and length of memory mapped
  9. region.
  10. - #clock-cells: should be 1.
  11. - #reset-cells: should be 1.
  12. Optional Properties:
  13. - rockchip,grf: phandle to the syscon managing the "general register files"
  14. If missing pll rates are not changable, due to the missing pll lock status.
  15. Each clock is assigned an identifier and client nodes can use this identifier
  16. to specify the clock which they consume. All available clocks are defined as
  17. preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
  18. dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
  19. Similar macros exist for the reset sources in these files.
  20. External clocks:
  21. There are several clocks that are generated outside the SoC. It is expected
  22. that they are defined using standard clock bindings with following
  23. clock-output-names:
  24. - "xin24m" - crystal input - required,
  25. - "xin32k" - rtc clock - optional,
  26. - "xin27m" - 27mhz crystal input on rk3066 - optional,
  27. - "ext_hsadc" - external HSADC clock - optional,
  28. - "ext_cif0" - external camera clock - optional,
  29. - "ext_rmii" - external RMII clock - optional,
  30. - "ext_jtag" - externalJTAG clock - optional
  31. Example: Clock controller node:
  32. cru: cru@20000000 {
  33. compatible = "rockchip,rk3188-cru";
  34. reg = <0x20000000 0x1000>;
  35. rockchip,grf = <&grf>;
  36. #clock-cells = <1>;
  37. #reset-cells = <1>;
  38. };
  39. Example: UART controller node that consumes the clock generated by the clock
  40. controller:
  41. uart0: serial@10124000 {
  42. compatible = "snps,dw-apb-uart";
  43. reg = <0x10124000 0x400>;
  44. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  45. reg-shift = <2>;
  46. reg-io-width = <1>;
  47. clocks = <&cru SCLK_UART0>;
  48. };