nvidia,tegra20-car.txt 3.6 KB

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  1. NVIDIA Tegra20 Clock And Reset Controller
  2. This binding uses the common clock binding:
  3. Documentation/devicetree/bindings/clock/clock-bindings.txt
  4. The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
  5. for muxing and gating Tegra's clocks, and setting their rates.
  6. Required properties :
  7. - compatible : Should be "nvidia,tegra20-car"
  8. - reg : Should contain CAR registers location and length
  9. - clocks : Should contain phandle and clock specifiers for two clocks:
  10. the 32 KHz "32k_in", and the board-specific oscillator "osc".
  11. - #clock-cells : Should be 1.
  12. In clock consumers, this cell represents the clock ID exposed by the CAR.
  13. The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
  14. registers. These IDs often match those in the CAR's RST_DEVICES registers,
  15. but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
  16. this case, those clocks are assigned IDs above 95 in order to highlight
  17. this issue. Implementations that interpret these clock IDs as bit values
  18. within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  19. explicitly handle these special cases.
  20. The balance of the clocks controlled by the CAR are assigned IDs of 96 and
  21. above.
  22. 0 cpu
  23. 1 unassigned
  24. 2 unassigned
  25. 3 ac97
  26. 4 rtc
  27. 5 tmr
  28. 6 uart1
  29. 7 unassigned (register bit affects uart2 and vfir)
  30. 8 gpio
  31. 9 sdmmc2
  32. 10 unassigned (register bit affects spdif_in and spdif_out)
  33. 11 i2s1
  34. 12 i2c1
  35. 13 ndflash
  36. 14 sdmmc1
  37. 15 sdmmc4
  38. 16 twc
  39. 17 pwm
  40. 18 i2s2
  41. 19 epp
  42. 20 unassigned (register bit affects vi and vi_sensor)
  43. 21 2d
  44. 22 usbd
  45. 23 isp
  46. 24 3d
  47. 25 ide
  48. 26 disp2
  49. 27 disp1
  50. 28 host1x
  51. 29 vcp
  52. 30 unassigned
  53. 31 cache2
  54. 32 mem
  55. 33 ahbdma
  56. 34 apbdma
  57. 35 unassigned
  58. 36 kbc
  59. 37 stat_mon
  60. 38 pmc
  61. 39 fuse
  62. 40 kfuse
  63. 41 sbc1
  64. 42 snor
  65. 43 spi1
  66. 44 sbc2
  67. 45 xio
  68. 46 sbc3
  69. 47 dvc
  70. 48 dsi
  71. 49 unassigned (register bit affects tvo and cve)
  72. 50 mipi
  73. 51 hdmi
  74. 52 csi
  75. 53 tvdac
  76. 54 i2c2
  77. 55 uart3
  78. 56 unassigned
  79. 57 emc
  80. 58 usb2
  81. 59 usb3
  82. 60 mpe
  83. 61 vde
  84. 62 bsea
  85. 63 bsev
  86. 64 speedo
  87. 65 uart4
  88. 66 uart5
  89. 67 i2c3
  90. 68 sbc4
  91. 69 sdmmc3
  92. 70 pcie
  93. 71 owr
  94. 72 afi
  95. 73 csite
  96. 74 unassigned
  97. 75 avpucq
  98. 76 la
  99. 77 unassigned
  100. 78 unassigned
  101. 79 unassigned
  102. 80 unassigned
  103. 81 unassigned
  104. 82 unassigned
  105. 83 unassigned
  106. 84 irama
  107. 85 iramb
  108. 86 iramc
  109. 87 iramd
  110. 88 cram2
  111. 89 audio_2x a/k/a audio_2x_sync_clk
  112. 90 clk_d
  113. 91 unassigned
  114. 92 sus
  115. 93 cdev1
  116. 94 cdev2
  117. 95 unassigned
  118. 96 uart2
  119. 97 vfir
  120. 98 spdif_in
  121. 99 spdif_out
  122. 100 vi
  123. 101 vi_sensor
  124. 102 tvo
  125. 103 cve
  126. 104 osc
  127. 105 clk_32k a/k/a clk_s
  128. 106 clk_m
  129. 107 sclk
  130. 108 cclk
  131. 109 hclk
  132. 110 pclk
  133. 111 blink
  134. 112 pll_a
  135. 113 pll_a_out0
  136. 114 pll_c
  137. 115 pll_c_out1
  138. 116 pll_d
  139. 117 pll_d_out0
  140. 118 pll_e
  141. 119 pll_m
  142. 120 pll_m_out1
  143. 121 pll_p
  144. 122 pll_p_out1
  145. 123 pll_p_out2
  146. 124 pll_p_out3
  147. 125 pll_p_out4
  148. 126 pll_s
  149. 127 pll_u
  150. 128 pll_x
  151. 129 cop a/k/a avp
  152. 130 audio a/k/a audio_sync_clk
  153. Example SoC include file:
  154. / {
  155. tegra_car: clock@60006000 {
  156. compatible = "nvidia,tegra20-car";
  157. reg = <0x60006000 0x1000>;
  158. #clock-cells = <1>;
  159. };
  160. usb@c5004000 {
  161. clocks = <&tegra_car 58>; /* usb2 */
  162. };
  163. };
  164. Example board file:
  165. / {
  166. clocks {
  167. #address-cells = <1>;
  168. #size-cells = <0>;
  169. osc: clock {
  170. compatible = "fixed-clock";
  171. #clock-cells = <0>;
  172. clock-frequency = <12000000>;
  173. };
  174. };
  175. i2c@7000d000 {
  176. pmic@34 {
  177. compatible = "ti,tps6586x";
  178. reg = <0x34>;
  179. clk_32k: clock {
  180. compatible = "fixed-clock";
  181. #clock-cells = <0>;
  182. clock-frequency = <32768>;
  183. };
  184. };
  185. };
  186. &tegra_car {
  187. clocks = <&clk_32k> <&osc>;
  188. };
  189. };