cougarcanyon2.rst 1.1 KB

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  1. .. SPDX-License-Identifier: GPL-2.0+
  2. .. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
  3. Cougar Canyon 2 CRB
  4. ===================
  5. This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
  6. with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
  7. website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
  8. time of writing) in the board directory and rename it to fsp.bin.
  9. Now build U-Boot and obtain u-boot.rom::
  10. $ make cougarcanyon2_defconfig
  11. $ make all
  12. The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
  13. the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
  14. and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
  15. flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
  16. this image to the SPI-0 flash according to the board manual just once and we are
  17. all set. For programming U-Boot we just need to program SPI-1 flash. Since the
  18. default u-boot.rom image for this board is set to 2MB, it should be programmed
  19. to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].