README.mpc85xx 5.9 KB

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  1. External Debug Support
  2. ----------------------
  3. Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
  4. restrictions on external debugging (JTAG). In particular, for the debugger to
  5. be able to receive control after a single step or breakpoint:
  6. - MSR[DE] must be set
  7. - A valid opcode must be fetchable, through the MMU, from the debug
  8. exception vector (IVPR + IVOR15).
  9. To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
  10. immediately on entry and keeps it set. It also uses a temporary TLB to keep a
  11. mapping to a valid opcode at the debug exception vector, even if we normally
  12. don't support exception vectors being used that early, and that's not the area
  13. where U-Boot currently executes from.
  14. Note that there may still be some small windows where debugging will not work,
  15. such as in between updating IVPR and IVOR15.
  16. Config Switches:
  17. ----------------
  18. Please refer README section "MPC85xx External Debug Support"
  19. Major Config Switches during various boot Modes
  20. ----------------------------------------------
  21. NOR boot
  22. !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
  23. NOR boot Secure
  24. !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
  25. RAMBOOT(SD, SPI & NAND boot)
  26. defined(CONFIG_SYS_RAMBOOT)
  27. RAMBOOT Secure (SD, SPI & NAND)
  28. defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
  29. NAND SPL BOOT
  30. defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
  31. TLB Entries during u-boot execution
  32. -----------------------------------
  33. Note: Sequence number is in order of execution
  34. A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
  35. 1) TLB entry to overcome e500 v1/v2 debug restriction
  36. Location : Label "_start_e500"
  37. TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
  38. EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
  39. Properties : 256K, AS0, I, IPROT
  40. 2) TLB entry for working in AS1
  41. Location : Label "create_init_ram_area"
  42. TLB Entry : 15
  43. EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
  44. Properties : 1M, AS1, I, G, IPROT
  45. 3) TLB entry for the stack during AS1
  46. Location : Lable "create_init_ram_area"
  47. TLB Entry : 14
  48. EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
  49. Properties : 16K, AS1, IPROT
  50. 4) TLB entry for CCSRBAR during AS1 execution
  51. Location : cpu_init_early_f
  52. TLB Entry : 13
  53. EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
  54. Properties : 1M, AS1, I, G
  55. 5) Invalidate unproctected TLB Entries
  56. Location : cpu_init_early_f
  57. Invalidated: 13
  58. 6) Create TLB entries as per boards/freescale/<board>/tlb.c
  59. Location : cpu_init_early_f --> init_tlbs()
  60. Properties : ..., AS0, ...
  61. Please note It can overwrites previous TLB Entries.
  62. 7) Disable TLB Entries of AS1
  63. Location : cpu_init_f --> disable_tlb()
  64. Disable : 15, 14
  65. 8) Update Flash's TLB entry
  66. Location : Board_init_r
  67. TLB entry : Search from TLB entries
  68. EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
  69. Properties : Board specific size, AS0, I, G, IPROT
  70. B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
  71. 1) TLB entry to overcome e500 v1/v2 debug restriction
  72. Location : Label "_start_e500"
  73. TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
  74. #if defined(CONFIG_NXP_ESBC)
  75. EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
  76. Properties : 1M, AS1, I, G, IPROT
  77. #else
  78. EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
  79. Properties : 4M, AS0, I, G, IPROT
  80. #endif
  81. 2) TLB entry for working in AS1
  82. Location : Label "create_init_ram_area"
  83. TLB Entry : 15
  84. #if defined(CONFIG_NXP_ESBC)
  85. EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
  86. Properties : 1M, AS1, I, G, IPROT
  87. #else
  88. EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
  89. Properties : 4M, AS1, I, G, IPROT
  90. #endif
  91. 3) TLB entry for the stack during AS1
  92. Location : Lable "create_init_ram_area"
  93. TLB Entry : 14
  94. EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
  95. Properties : 16K, AS1, IPROT
  96. 4) TLB entry for CCSRBAR during AS1 execution
  97. Location : cpu_init_early_f
  98. TLB Entry : 13
  99. EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
  100. Properties : 1M, AS1, I, G
  101. 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  102. Location : cpu_init_early_f
  103. TLB Entry : 9
  104. EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR
  105. Properties : 1M, AS1, I
  106. 6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr
  107. Location : cpu_init_early_f --> setup_ifc
  108. TLB Entry : Get Flash TLB
  109. EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
  110. Properties : 4M, AS1, I, G, IPROT
  111. 7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction
  112. Location : cpu_init_early_f --> setup_ifc
  113. TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
  114. EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
  115. Properties : 4M, AS0, I, G, IPROT
  116. 8) Invalidate unproctected TLB Entries
  117. Location : cpu_init_early_f
  118. Invalidated: 13, 9
  119. 9) Create TLB entries as per boards/freescale/<board>/tlb.c
  120. Location : cpu_init_early_f --> init_tlbs()
  121. Properties : ..., AS0, ...
  122. Note: It can overwrites previous TLB Entries
  123. 10) Disable TLB Entries of AS1
  124. Location : cpu_init_f --> disable_tlb()
  125. Disable : 15, 14
  126. 11) Create DDR's TLB entriy
  127. Location : Board_init_f -> dram_init
  128. TLB entry : Search free TLB entry
  129. 12) Update Flash's TLB entry
  130. Location : Board_init_r
  131. TLB entry : Search from TLB entries
  132. EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
  133. Properties : Board specific size, AS0, I, G, IPROT