README.fsl-ddr 21 KB

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  1. Table of interleaving 2-4 controllers
  2. =====================================
  3. +--------------+-----------------------------------------------------------+
  4. |Configuration | Memory Controller |
  5. | | 1 2 3 4 |
  6. |--------------+--------------+--------------+-----------------------------+
  7. | Two memory | Not Intlv'ed | Not Intlv'ed | |
  8. | complexes +--------------+--------------+ |
  9. | | 2-way Intlv'ed | |
  10. |--------------+--------------+--------------+--------------+ |
  11. | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | |
  12. | Three memory +--------------+--------------+--------------+ |
  13. | complexes | 2-way Intlv'ed | Not Intlv'ed | |
  14. | +-----------------------------+--------------+ |
  15. | | 3-way Intlv'ed | |
  16. +--------------+--------------+--------------+--------------+--------------+
  17. | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
  18. | Four memory +--------------+--------------+--------------+--------------+
  19. | complexes | 2-way Intlv'ed | 2-way Intlv'ed |
  20. | +-----------------------------+-----------------------------+
  21. | | 4-way Intlv'ed |
  22. +--------------+-----------------------------------------------------------+
  23. Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
  24. ======================================================
  25. +-------------+---------------------------------------------------------+
  26. | | Rank Interleaving |
  27. | +--------+-----------+-----------+------------+-----------+
  28. |Memory | | | | 2x2 | 4x1 |
  29. |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
  30. |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
  31. +-------------+--------+-----------+-----------+------------+-----------+
  32. |None | Yes | Yes | Yes | Yes | Yes |
  33. +-------------+--------+-----------+-----------+------------+-----------+
  34. |Cacheline | Yes | Yes | No | No, Only(*)| Yes |
  35. | |CS0 Only| | | {CS0+CS1} | |
  36. +-------------+--------+-----------+-----------+------------+-----------+
  37. |Page | Yes | Yes | No | No, Only(*)| Yes |
  38. | |CS0 Only| | | {CS0+CS1} | |
  39. +-------------+--------+-----------+-----------+------------+-----------+
  40. |Bank | Yes | Yes | No | No, Only(*)| Yes |
  41. | |CS0 Only| | | {CS0+CS1} | |
  42. +-------------+--------+-----------+-----------+------------+-----------+
  43. |Superbank | No | Yes | No | No, Only(*)| Yes |
  44. | | | | | {CS0+CS1} | |
  45. +-------------+--------+-----------+-----------+------------+-----------+
  46. (*) Although the hardware can be configured with memory controller
  47. interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
  48. from each controller. {CS2+CS3} on each controller are only rank
  49. interleaved on that controller.
  50. For memory controller interleaving, identical DIMMs are suggested. Software
  51. doesn't check the size or organization of interleaved DIMMs.
  52. The ways to configure the ddr interleaving mode
  53. ==============================================
  54. 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
  55. under "CONFIG_EXTRA_ENV_SETTINGS", like:
  56. #define CONFIG_EXTRA_ENV_SETTINGS \
  57. "hwconfig=fsl_ddr:ctlr_intlv=bank" \
  58. ......
  59. 2. Run U-Boot "setenv" command to configure the memory interleaving mode.
  60. Either numerical or string value is accepted.
  61. # disable memory controller interleaving
  62. setenv hwconfig "fsl_ddr:ctlr_intlv=null"
  63. # cacheline interleaving
  64. setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
  65. # page interleaving
  66. setenv hwconfig "fsl_ddr:ctlr_intlv=page"
  67. # bank interleaving
  68. setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
  69. # superbank
  70. setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
  71. # 1KB 3-way interleaving
  72. setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
  73. # 4KB 3-way interleaving
  74. setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
  75. # 8KB 3-way interleaving
  76. setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
  77. # disable bank (chip-select) interleaving
  78. setenv hwconfig "fsl_ddr:bank_intlv=null"
  79. # bank(chip-select) interleaving cs0+cs1
  80. setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
  81. # bank(chip-select) interleaving cs2+cs3
  82. setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
  83. # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
  84. setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
  85. # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
  86. setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
  87. # bank(chip-select) interleaving (auto)
  88. setenv hwconfig "fsl_ddr:bank_intlv=auto"
  89. This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
  90. on DIMMs.
  91. Memory controller address hashing
  92. ==================================
  93. If the DDR controller supports address hashing, it can be enabled by hwconfig.
  94. Syntax is:
  95. hwconfig=fsl_ddr:addr_hash=true
  96. Memory controller ECC on/off
  97. ============================
  98. If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
  99. ECC can be turned on/off by hwconfig.
  100. Syntax is
  101. hwconfig=fsl_ddr:ecc=off
  102. Memory address parity on/off
  103. ============================
  104. address parity can be turned on/off by hwconfig.
  105. Syntax is:
  106. hwconfig=fsl_ddr:parity=on
  107. Memory testing options for mpc85xx
  108. ==================================
  109. 1. Memory test can be done once U-Boot prompt comes up using mtest, or
  110. 2. Memory test can be done with Power-On-Self-Test function, activated at
  111. compile time.
  112. In order to enable the POST memory test, CONFIG_POST needs to be
  113. defined in board configuraiton header file. By default, POST memory test
  114. performs a fast test. A slow test can be enabled by changing the flag at
  115. compiling time. To test memory bigger than 2GB, 36BIT support is needed.
  116. Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
  117. window to physical address so that all physical memory can be tested.
  118. Combination of hwconfig
  119. =======================
  120. Hwconfig can be combined with multiple parameters, for example, on a supported
  121. platform
  122. hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
  123. Table for dynamic ODT for DDR3
  124. ==============================
  125. For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
  126. be needed, depending on the configuration. The numbers in the following tables are
  127. in Ohms.
  128. * denotes dynamic ODT
  129. Two slots system
  130. +-----------------------+----------+---------------+-----------------------------+-----------------------------+
  131. | Configuration | |DRAM controller| Slot 1 | Slot 2 |
  132. +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
  133. | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
  134. + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
  135. | | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
  136. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  137. | | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 |
  138. | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  139. | | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off |
  140. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  141. | | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | |
  142. | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  143. | | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | |
  144. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  145. | | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 |
  146. |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  147. | | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off |
  148. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  149. | | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | |
  150. |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  151. | | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | |
  152. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  153. | Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | |
  154. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  155. | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off |
  156. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  157. |Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | |
  158. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  159. | Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | |
  160. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  161. Single slot system
  162. +-------------+------------+---------------+-----------------------------+-----------------------------+
  163. | | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 |
  164. |Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
  165. | | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read |
  166. +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  167. | | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off |
  168. | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  169. | | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off |
  170. | Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  171. | | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off |
  172. | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  173. | | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off |
  174. +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  175. | | R1 | off | 75 | 40 | off | off | off |
  176. | Dual Rank |------------+-------+-------+-------+------+-------+------+
  177. | | R2 | off | 75 | 40 | off | off | off |
  178. +-------------+------------+-------+-------+-------+------+-------+------+
  179. | Single Rank | R1 | off | 75 | 40 | off |
  180. +-------------+------------+-------+-------+-------+------+
  181. Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
  182. http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
  183. Table for ODT for DDR2
  184. ======================
  185. Two slots system
  186. +-----------------------+----------+---------------+-----------------------------+-----------------------------+
  187. | Configuration | |DRAM controller| Slot 1 | Slot 2 |
  188. +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
  189. | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
  190. + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
  191. | | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
  192. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  193. | | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | off | off |
  194. | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  195. | | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | off | off |
  196. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  197. | | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | | |
  198. | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  199. | | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | | |
  200. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  201. | | | Slot 1 | off | 150 | off | off | | | 75 | 75 | off | off |
  202. |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  203. | | | Slot 2 | off | 150 | 75 | 75 | | | off | off | off | off |
  204. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  205. | | | Slot 1 | off | 150 | off | off | | | 75 | 75 | | |
  206. |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  207. | | | Slot 2 | off | 150 | 75 | 75 | | | off | off | | |
  208. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  209. | Dual Rank | Empty | Slot 1 | off | 75 | 150 | off | off | off | | | | |
  210. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  211. | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 150 | off | off | off |
  212. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  213. |Single Rank| Empty | Slot 1 | off | 75 | 150 | off | | | | | | |
  214. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  215. | Empty |Single Rank| Slot 2 | off | 75 | | | | | 150 | off | | |
  216. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  217. Single slot system
  218. +-------------+------------+---------------+-----------------------------+
  219. | | |DRAM controller| Rank 1 | Rank 2 |
  220. |Configuration| Write/Read |-------+-------+-------+------+-------+------+
  221. | | | Write | Read | Write | Read | Write | Read |
  222. +-------------+------------+-------+-------+-------+------+-------+------+
  223. | | R1 | off | 75 | 150 | off | off | off |
  224. | Dual Rank |------------+-------+-------+-------+------+-------+------+
  225. | | R2 | off | 75 | 150 | off | off | off |
  226. +-------------+------------+-------+-------+-------+------+-------+------+
  227. | Single Rank | R1 | off | 75 | 150 | off |
  228. +-------------+------------+-------+-------+-------+------+
  229. Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
  230. Interactive DDR debugging
  231. ===========================
  232. For DDR parameter tuning up and debugging, the interactive DDR debugger can
  233. be activated by setting the environment variable "ddr_interactive" to any
  234. value. (The value of ddr_interactive may have a meaning in the future, but,
  235. for now, the presence of the variable will cause the debugger to run.) Once
  236. activated, U-Boot will show the prompt "FSL DDR>" before enabling the DDR
  237. controller. The available commands are printed by typing "help".
  238. Another way to enter the interactive DDR debugger without setting the
  239. environment variable is to send the 'd' character early during the boot
  240. process. To save booting time, no additional delay is added, so the window
  241. to send the key press is very short -- basically, it is the time before the
  242. memory controller code starts to run. For example, when rebooting from
  243. within U-Boot, the user must press 'd' IMMEDIATELY after hitting enter to
  244. initiate a 'reset' command. In case of power on/reset, the user can hold
  245. down the 'd' key while applying power or hitting the board's reset button.
  246. The example flow of using interactive debugging is
  247. type command "compute" to calculate the parameters from the default
  248. type command "print" with arguments to show SPD, options, registers
  249. type command "edit" with arguments to change any if desired
  250. type command "copy" with arguments to copy controller/dimm settings
  251. type command "go" to continue calculation and enable DDR controller
  252. Additional commands to restart the debugging are:
  253. type command "reset" to reset the board
  254. type command "recompute" to reload SPD and start over
  255. Note, check "next_step" to show the flow. For example, after edit opts, the
  256. next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
  257. STEP_PROGRAM_REGS. Upon issuing command "go", the debugger will program the
  258. DDR controller with the current setting without further calculation and then
  259. exit to resume the booting of the machine.
  260. The detail syntax for each commands are
  261. print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
  262. c<n> - the controller number, eg. c0, c1
  263. d<n> - the DIMM number, eg. d0, d1
  264. spd - print SPD data
  265. dimmparms - DIMM parameters, calculated from SPD
  266. commonparms - lowest common parameters for all DIMMs
  267. opts - options
  268. addresses - address assignment (not implemented yet)
  269. regs - controller registers
  270. edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
  271. c<n> - the controller number, eg. c0, c1
  272. d<n> - the DIMM number, eg. d0, d1
  273. spd - print SPD data
  274. dimmparms - DIMM parameters, calculated from SPD
  275. commonparms - lowest common parameters for all DIMMs
  276. opts - options
  277. addresses - address assignment (not implemented yet)
  278. regs - controller registers
  279. <element> - name of the modified element
  280. byte number if the object is SPD
  281. <value> - decimal or heximal (prefixed with 0x) numbers
  282. copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>
  283. same as for "edit" command
  284. DIMM numbers ignored for commonparms, opts, and regs
  285. reset
  286. no arguement - reset the board
  287. recompute
  288. no argument - reload SPD and start over
  289. compute
  290. no argument - recompute from current next_step
  291. next_step
  292. no argument - show current next_step
  293. help
  294. no argument - print a list of all commands
  295. go
  296. no argument - program memory controller(s) and continue with U-Boot
  297. Examples of debugging flow
  298. FSL DDR>compute
  299. Detected UDIMM UG51U6400N8SU-ACF
  300. FSL DDR>print
  301. print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
  302. FSL DDR>print dimmparms
  303. DIMM parameters: Controller=0 DIMM=0
  304. DIMM organization parameters:
  305. module part name = UG51U6400N8SU-ACF
  306. rank_density = 2147483648 bytes (2048 megabytes)
  307. capacity = 4294967296 bytes (4096 megabytes)
  308. burst_lengths_bitmask = 0C
  309. base_addresss = 0 (00000000 00000000)
  310. n_ranks = 2
  311. data_width = 64
  312. primary_sdram_width = 64
  313. ec_sdram_width = 0
  314. registered_dimm = 0
  315. n_row_addr = 15
  316. n_col_addr = 10
  317. edc_config = 0
  318. n_banks_per_sdram_device = 8
  319. tCKmin_X_ps = 1500
  320. tCKmin_X_minus_1_ps = 0
  321. tCKmin_X_minus_2_ps = 0
  322. tCKmax_ps = 0
  323. caslat_X = 960
  324. tAA_ps = 13125
  325. caslat_X_minus_1 = 0
  326. caslat_X_minus_2 = 0
  327. caslat_lowest_derated = 0
  328. tRCD_ps = 13125
  329. tRP_ps = 13125
  330. tRAS_ps = 36000
  331. tWR_ps = 15000
  332. tWTR_ps = 7500
  333. tRFC_ps = 160000
  334. tRRD_ps = 6000
  335. tRC_ps = 49125
  336. refresh_rate_ps = 7800000
  337. tIS_ps = 0
  338. tIH_ps = 0
  339. tDS_ps = 0
  340. tDH_ps = 0
  341. tRTP_ps = 7500
  342. tDQSQ_max_ps = 0
  343. tQHS_ps = 0
  344. FSL DDR>edit c0 opts ECC_mode 0
  345. FSL DDR>edit c0 regs cs0_bnds 0x000000FF
  346. FSL DDR>go
  347. 2 GiB left unmapped
  348. 4 GiB (DDR3, 64-bit, CL=9, ECC off)
  349. DDR Chip-Select Interleaving Mode: CS0+CS1
  350. Testing 0x00000000 - 0x7fffffff
  351. Testing 0x80000000 - 0xffffffff
  352. Remap DDR 2 GiB left unmapped
  353. POST memory PASSED
  354. Flash: 128 MiB
  355. L2: 128 KB enabled
  356. Corenet Platform Cache: 1024 KB enabled
  357. SERDES: timeout resetting bank 3
  358. SRIO1: disabled
  359. SRIO2: disabled
  360. MMC: FSL_ESDHC: 0
  361. EEPROM: Invalid ID (ff ff ff ff)
  362. PCIe1: disabled
  363. PCIe2: Root Complex, x1, regs @ 0xfe201000
  364. 01:00.0 - 8086:10d3 - Network controller
  365. PCIe2: Bus 00 - 01
  366. PCIe3: disabled
  367. In: serial
  368. Out: serial
  369. Err: serial
  370. Net: Initializing Fman
  371. Fman1: Uploading microcode version 101.8.0
  372. e1000: 00:1b:21:81:d2:e0
  373. FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
  374. Warning: e1000#0 MAC addresses don't match:
  375. Address in SROM is 00:1b:21:81:d2:e0
  376. Address in environment is 00:e0:0c:00:ea:05
  377. Hit any key to stop autoboot: 0
  378. =>