wandboard.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2014 O.S. Systems Software LTDA.
  5. *
  6. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <image.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/imx-regs.h>
  16. #include <asm/arch/mx6-pins.h>
  17. #include <asm/arch/mxc_hdmi.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/gpio.h>
  20. #include <asm/mach-imx/iomux-v3.h>
  21. #include <asm/mach-imx/mxc_i2c.h>
  22. #include <asm/mach-imx/boot_mode.h>
  23. #include <asm/mach-imx/video.h>
  24. #include <asm/mach-imx/sata.h>
  25. #include <asm/io.h>
  26. #include <env.h>
  27. #include <linux/delay.h>
  28. #include <linux/sizes.h>
  29. #include <common.h>
  30. #include <miiphy.h>
  31. #include <netdev.h>
  32. #include <phy.h>
  33. #include <i2c.h>
  34. #include <power/pmic.h>
  35. #include <power/pfuze100_pmic.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  38. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  39. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  40. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  41. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  42. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  43. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  44. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  45. #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
  46. #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
  47. #define REV_DETECTION IMX_GPIO_NR(2, 28)
  48. /* Speed defined in Kconfig is only applicable when not using DM_I2C. */
  49. #ifdef CONFIG_DM_I2C
  50. #define I2C1_SPEED_NON_DM 0
  51. #define I2C2_SPEED_NON_DM 0
  52. #else
  53. #define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
  54. #define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
  55. #endif
  56. static bool with_pmic;
  57. int dram_init(void)
  58. {
  59. gd->ram_size = imx_ddr_size();
  60. return 0;
  61. }
  62. static iomux_v3_cfg_t const uart1_pads[] = {
  63. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  64. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  65. };
  66. static iomux_v3_cfg_t const enet_pads[] = {
  67. /* AR8031 PHY Reset */
  68. IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  69. };
  70. static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
  71. /* AR8035 POWER */
  72. IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  73. };
  74. static iomux_v3_cfg_t const rev_detection_pad[] = {
  75. IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  76. };
  77. static void setup_iomux_uart(void)
  78. {
  79. SETUP_IOMUX_PADS(uart1_pads);
  80. }
  81. static void setup_iomux_enet(void)
  82. {
  83. SETUP_IOMUX_PADS(enet_pads);
  84. if (with_pmic) {
  85. SETUP_IOMUX_PADS(enet_ar8035_power_pads);
  86. /* enable AR8035 POWER */
  87. gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
  88. gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
  89. }
  90. /* wait until 3.3V of PHY and clock become stable */
  91. mdelay(10);
  92. /* Reset AR8031 PHY */
  93. gpio_request(ETH_PHY_RESET, "PHY_RESET");
  94. gpio_direction_output(ETH_PHY_RESET, 0);
  95. mdelay(10);
  96. gpio_set_value(ETH_PHY_RESET, 1);
  97. udelay(100);
  98. }
  99. static int ar8031_phy_fixup(struct phy_device *phydev)
  100. {
  101. unsigned short val;
  102. int mask;
  103. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  104. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  105. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  106. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  107. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  108. if (with_pmic)
  109. mask = 0xffe7; /* AR8035 */
  110. else
  111. mask = 0xffe3; /* AR8031 */
  112. val &= mask;
  113. val |= 0x18;
  114. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  115. /* introduce tx clock delay */
  116. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  117. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  118. val |= 0x0100;
  119. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  120. return 0;
  121. }
  122. int board_phy_config(struct phy_device *phydev)
  123. {
  124. ar8031_phy_fixup(phydev);
  125. if (phydev->drv->config)
  126. phydev->drv->config(phydev);
  127. return 0;
  128. }
  129. #if defined(CONFIG_VIDEO_IPUV3)
  130. struct i2c_pads_info mx6q_i2c2_pad_info = {
  131. .scl = {
  132. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
  133. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  134. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
  135. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  136. .gp = IMX_GPIO_NR(4, 12)
  137. },
  138. .sda = {
  139. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
  140. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  141. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
  142. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  143. .gp = IMX_GPIO_NR(4, 13)
  144. }
  145. };
  146. struct i2c_pads_info mx6dl_i2c2_pad_info = {
  147. .scl = {
  148. .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
  149. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  150. .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
  151. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  152. .gp = IMX_GPIO_NR(4, 12)
  153. },
  154. .sda = {
  155. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
  156. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  157. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
  158. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  159. .gp = IMX_GPIO_NR(4, 13)
  160. }
  161. };
  162. struct i2c_pads_info mx6q_i2c3_pad_info = {
  163. .scl = {
  164. .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
  165. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  166. .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
  167. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  168. .gp = IMX_GPIO_NR(1, 5)
  169. },
  170. .sda = {
  171. .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
  172. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  173. .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
  174. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  175. .gp = IMX_GPIO_NR(7, 11)
  176. }
  177. };
  178. struct i2c_pads_info mx6dl_i2c3_pad_info = {
  179. .scl = {
  180. .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
  181. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  182. .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
  183. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  184. .gp = IMX_GPIO_NR(1, 5)
  185. },
  186. .sda = {
  187. .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
  188. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  189. .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
  190. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  191. .gp = IMX_GPIO_NR(7, 11)
  192. }
  193. };
  194. static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
  195. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
  196. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
  197. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
  198. IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
  199. IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
  200. IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
  201. IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
  202. IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
  203. IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
  204. IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
  205. IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
  206. IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
  207. IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
  208. IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
  209. IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
  210. IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
  211. IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
  212. IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
  213. IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
  214. IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
  215. IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
  216. IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
  217. IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
  218. IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
  219. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
  220. };
  221. static void do_enable_hdmi(struct display_info_t const *dev)
  222. {
  223. imx_enable_hdmi_phy();
  224. }
  225. static int detect_i2c(struct display_info_t const *dev)
  226. {
  227. #ifdef CONFIG_DM_I2C
  228. struct udevice *bus, *udev;
  229. int rc;
  230. rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
  231. if (rc)
  232. return rc;
  233. rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
  234. if (rc)
  235. return 0;
  236. return 1;
  237. #else
  238. return (0 == i2c_set_bus_num(dev->bus)) &&
  239. (0 == i2c_probe(dev->addr));
  240. #endif
  241. }
  242. static void enable_fwadapt_7wvga(struct display_info_t const *dev)
  243. {
  244. SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
  245. gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
  246. gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
  247. gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
  248. gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
  249. }
  250. struct display_info_t const displays[] = {{
  251. .bus = -1,
  252. .addr = 0,
  253. .pixfmt = IPU_PIX_FMT_RGB24,
  254. .detect = detect_hdmi,
  255. .enable = do_enable_hdmi,
  256. .mode = {
  257. .name = "HDMI",
  258. .refresh = 60,
  259. .xres = 1024,
  260. .yres = 768,
  261. .pixclock = 15385,
  262. .left_margin = 220,
  263. .right_margin = 40,
  264. .upper_margin = 21,
  265. .lower_margin = 7,
  266. .hsync_len = 60,
  267. .vsync_len = 10,
  268. .sync = FB_SYNC_EXT,
  269. .vmode = FB_VMODE_NONINTERLACED
  270. } }, {
  271. .bus = 1,
  272. .addr = 0x10,
  273. .pixfmt = IPU_PIX_FMT_RGB666,
  274. .detect = detect_i2c,
  275. .enable = enable_fwadapt_7wvga,
  276. .mode = {
  277. .name = "FWBADAPT-LCD-F07A-0102",
  278. .refresh = 60,
  279. .xres = 800,
  280. .yres = 480,
  281. .pixclock = 33260,
  282. .left_margin = 128,
  283. .right_margin = 128,
  284. .upper_margin = 22,
  285. .lower_margin = 22,
  286. .hsync_len = 1,
  287. .vsync_len = 1,
  288. .sync = 0,
  289. .vmode = FB_VMODE_NONINTERLACED
  290. } } };
  291. size_t display_count = ARRAY_SIZE(displays);
  292. static void setup_display(void)
  293. {
  294. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  295. int reg;
  296. enable_ipu_clock();
  297. imx_setup_hdmi();
  298. reg = readl(&mxc_ccm->chsccdr);
  299. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  300. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  301. writel(reg, &mxc_ccm->chsccdr);
  302. /* Disable LCD backlight */
  303. SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
  304. gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
  305. gpio_direction_input(IMX_GPIO_NR(4, 20));
  306. }
  307. #endif /* CONFIG_VIDEO_IPUV3 */
  308. int board_early_init_f(void)
  309. {
  310. setup_iomux_uart();
  311. #ifdef CONFIG_SATA
  312. setup_sata();
  313. #endif
  314. return 0;
  315. }
  316. #define PMIC_I2C_BUS 2
  317. int power_init_board(void)
  318. {
  319. struct udevice *dev;
  320. int reg, ret;
  321. ret = pmic_get("pfuze100@8", &dev);
  322. if (ret < 0) {
  323. debug("pmic_get() ret %d\n", ret);
  324. return 0;
  325. }
  326. reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
  327. if (reg < 0) {
  328. debug("pmic_reg_read() ret %d\n", reg);
  329. return 0;
  330. }
  331. printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
  332. with_pmic = true;
  333. /* Set VGEN2 to 1.5V and enable */
  334. reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
  335. reg &= ~(LDO_VOL_MASK);
  336. reg |= (LDOA_1_50V | (1 << (LDO_EN)));
  337. pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
  338. return 0;
  339. }
  340. /*
  341. * Do not overwrite the console
  342. * Use always serial for U-Boot console
  343. */
  344. int overwrite_console(void)
  345. {
  346. return 1;
  347. }
  348. #ifdef CONFIG_CMD_BMODE
  349. static const struct boot_mode board_boot_modes[] = {
  350. /* 4 bit bus width */
  351. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  352. {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  353. {NULL, 0},
  354. };
  355. #endif
  356. static bool is_revc1(void)
  357. {
  358. SETUP_IOMUX_PADS(rev_detection_pad);
  359. gpio_request(REV_DETECTION, "REV_DETECT");
  360. gpio_direction_input(REV_DETECTION);
  361. if (gpio_get_value(REV_DETECTION))
  362. return true;
  363. else
  364. return false;
  365. }
  366. static bool is_revd1(void)
  367. {
  368. if (with_pmic)
  369. return true;
  370. else
  371. return false;
  372. }
  373. int board_late_init(void)
  374. {
  375. #ifdef CONFIG_CMD_BMODE
  376. add_board_boot_modes(board_boot_modes);
  377. #endif
  378. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  379. if (is_mx6dqp())
  380. env_set("board_rev", "MX6QP");
  381. else if (is_mx6dq())
  382. env_set("board_rev", "MX6Q");
  383. else
  384. env_set("board_rev", "MX6DL");
  385. if (is_revd1())
  386. env_set("board_name", "D1");
  387. else if (is_revc1())
  388. env_set("board_name", "C1");
  389. else
  390. env_set("board_name", "B1");
  391. #endif
  392. setup_iomux_enet();
  393. if (is_revd1())
  394. puts("Board: Wandboard rev D1\n");
  395. else if (is_revc1())
  396. puts("Board: Wandboard rev C1\n");
  397. else
  398. puts("Board: Wandboard rev B1\n");
  399. return 0;
  400. }
  401. int board_init(void)
  402. {
  403. /* address of boot parameters */
  404. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  405. #if defined(CONFIG_VIDEO_IPUV3)
  406. setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
  407. if (is_mx6dq() || is_mx6dqp()) {
  408. setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
  409. setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
  410. } else {
  411. setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
  412. setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
  413. }
  414. setup_display();
  415. #endif
  416. return 0;
  417. }
  418. #ifdef CONFIG_SPL_LOAD_FIT
  419. int board_fit_config_name_match(const char *name)
  420. {
  421. if (is_mx6dq()) {
  422. if (!strcmp(name, "imx6q-wandboard-revd1"))
  423. return 0;
  424. } else if (is_mx6dqp()) {
  425. if (!strcmp(name, "imx6qp-wandboard-revd1"))
  426. return 0;
  427. } else if (is_mx6dl() || is_mx6solo()) {
  428. if (!strcmp(name, "imx6dl-wandboard-revd1"))
  429. return 0;
  430. }
  431. return -EINVAL;
  432. }
  433. #endif