board.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM335X based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <net.h>
  14. #include <serial.h>
  15. #include <linux/libfdt.h>
  16. #include <spl.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/omap.h>
  20. #include <asm/arch/ddr_defs.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/mmc_host_def.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/arch/mem.h>
  26. #include <asm/arch/mux.h>
  27. #include <asm/io.h>
  28. #include <asm/emif.h>
  29. #include <asm/gpio.h>
  30. #include <i2c.h>
  31. #include <miiphy.h>
  32. #include <cpsw.h>
  33. #include <power/tps65910.h>
  34. #include <watchdog.h>
  35. #include "board.h"
  36. DECLARE_GLOBAL_DATA_PTR;
  37. /* GPIO that controls DIP switch and mPCIe slot */
  38. #define DIP_S1 44
  39. #define MPCIE_SW 100
  40. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  41. static int baltos_set_console(void)
  42. {
  43. int val, i, dips = 0;
  44. char buf[7];
  45. for (i = 0; i < 4; i++) {
  46. sprintf(buf, "dip_s%d", i + 1);
  47. if (gpio_request(DIP_S1 + i, buf)) {
  48. printf("failed to export GPIO %d\n", DIP_S1 + i);
  49. return 0;
  50. }
  51. if (gpio_direction_input(DIP_S1 + i)) {
  52. printf("failed to set GPIO %d direction\n", DIP_S1 + i);
  53. return 0;
  54. }
  55. val = gpio_get_value(DIP_S1 + i);
  56. dips |= val << i;
  57. }
  58. printf("DIPs: 0x%1x\n", (~dips) & 0xf);
  59. if ((dips & 0xf) == 0xe)
  60. env_set("console", "ttyUSB0,115200n8");
  61. return 0;
  62. }
  63. static int read_eeprom(BSP_VS_HWPARAM *header)
  64. {
  65. i2c_set_bus_num(1);
  66. /* Check if baseboard eeprom is available */
  67. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  68. puts("Could not probe the EEPROM; something fundamentally "
  69. "wrong on the I2C bus.\n");
  70. return -ENODEV;
  71. }
  72. /* read the eeprom using i2c */
  73. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  74. sizeof(BSP_VS_HWPARAM))) {
  75. puts("Could not read the EEPROM; something fundamentally"
  76. " wrong on the I2C bus.\n");
  77. return -EIO;
  78. }
  79. if (header->Magic != 0xDEADBEEF) {
  80. printf("Incorrect magic number (0x%x) in EEPROM\n",
  81. header->Magic);
  82. /* fill default values */
  83. header->SystemId = 211;
  84. header->MAC1[0] = 0x00;
  85. header->MAC1[1] = 0x00;
  86. header->MAC1[2] = 0x00;
  87. header->MAC1[3] = 0x00;
  88. header->MAC1[4] = 0x00;
  89. header->MAC1[5] = 0x01;
  90. header->MAC2[0] = 0x00;
  91. header->MAC2[1] = 0x00;
  92. header->MAC2[2] = 0x00;
  93. header->MAC2[3] = 0x00;
  94. header->MAC2[4] = 0x00;
  95. header->MAC2[5] = 0x02;
  96. header->MAC3[0] = 0x00;
  97. header->MAC3[1] = 0x00;
  98. header->MAC3[2] = 0x00;
  99. header->MAC3[3] = 0x00;
  100. header->MAC3[4] = 0x00;
  101. header->MAC3[5] = 0x03;
  102. }
  103. return 0;
  104. }
  105. #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
  106. static const struct ddr_data ddr3_baltos_data = {
  107. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  108. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  109. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  110. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  111. };
  112. static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
  113. .cmd0csratio = MT41K256M16HA125E_RATIO,
  114. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  115. .cmd1csratio = MT41K256M16HA125E_RATIO,
  116. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  117. .cmd2csratio = MT41K256M16HA125E_RATIO,
  118. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  119. };
  120. static struct emif_regs ddr3_baltos_emif_reg_data = {
  121. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  122. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  123. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  124. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  125. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  126. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  127. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  128. };
  129. #ifdef CONFIG_SPL_OS_BOOT
  130. int spl_start_uboot(void)
  131. {
  132. /* break into full u-boot on 'c' */
  133. return (serial_tstc() && serial_getc() == 'c');
  134. }
  135. #endif
  136. #define OSC (V_OSCK/1000000)
  137. const struct dpll_params dpll_ddr = {
  138. 266, OSC-1, 1, -1, -1, -1, -1};
  139. const struct dpll_params dpll_ddr_evm_sk = {
  140. 303, OSC-1, 1, -1, -1, -1, -1};
  141. const struct dpll_params dpll_ddr_baltos = {
  142. 400, OSC-1, 1, -1, -1, -1, -1};
  143. void am33xx_spl_board_init(void)
  144. {
  145. int mpu_vdd;
  146. int sil_rev;
  147. /* Get the frequency */
  148. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  149. /*
  150. * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
  151. * MPU frequencies we support we use a CORE voltage of
  152. * 1.1375V. For MPU voltage we need to switch based on
  153. * the frequency we are running at.
  154. */
  155. i2c_set_bus_num(1);
  156. printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
  157. if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
  158. puts("i2c: cannot access TPS65910\n");
  159. return;
  160. }
  161. /*
  162. * Depending on MPU clock and PG we will need a different
  163. * VDD to drive at that speed.
  164. */
  165. sil_rev = readl(&cdev->deviceid) >> 28;
  166. mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
  167. dpll_mpu_opp100.m);
  168. /* Tell the TPS65910 to use i2c */
  169. tps65910_set_i2c_control();
  170. /* First update MPU voltage. */
  171. if (tps65910_voltage_update(MPU, mpu_vdd))
  172. return;
  173. /* Second, update the CORE voltage. */
  174. if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
  175. return;
  176. /* Set CORE Frequencies to OPP100 */
  177. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  178. /* Set MPU Frequency to what we detected now that voltages are set */
  179. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  180. writel(0x000010ff, PRM_DEVICE_INST + 4);
  181. }
  182. const struct dpll_params *get_dpll_ddr_params(void)
  183. {
  184. enable_i2c1_pin_mux();
  185. i2c_set_bus_num(1);
  186. return &dpll_ddr_baltos;
  187. }
  188. void set_uart_mux_conf(void)
  189. {
  190. enable_uart0_pin_mux();
  191. }
  192. void set_mux_conf_regs(void)
  193. {
  194. enable_board_pin_mux();
  195. }
  196. const struct ctrl_ioregs ioregs_baltos = {
  197. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  198. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  199. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  200. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  201. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  202. };
  203. void sdram_init(void)
  204. {
  205. config_ddr(400, &ioregs_baltos,
  206. &ddr3_baltos_data,
  207. &ddr3_baltos_cmd_ctrl_data,
  208. &ddr3_baltos_emif_reg_data, 0);
  209. }
  210. #endif
  211. /*
  212. * Basic board specific setup. Pinmux has been handled already.
  213. */
  214. int board_init(void)
  215. {
  216. #if defined(CONFIG_HW_WATCHDOG)
  217. hw_watchdog_init();
  218. #endif
  219. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  220. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  221. gpmc_init();
  222. #endif
  223. return 0;
  224. }
  225. int ft_board_setup(void *blob, struct bd_info *bd)
  226. {
  227. int node, ret;
  228. unsigned char mac_addr[6];
  229. BSP_VS_HWPARAM header;
  230. /* get production data */
  231. if (read_eeprom(&header))
  232. return 0;
  233. /* setup MAC1 */
  234. mac_addr[0] = header.MAC1[0];
  235. mac_addr[1] = header.MAC1[1];
  236. mac_addr[2] = header.MAC1[2];
  237. mac_addr[3] = header.MAC1[3];
  238. mac_addr[4] = header.MAC1[4];
  239. mac_addr[5] = header.MAC1[5];
  240. node = fdt_path_offset(blob, "ethernet0");
  241. if (node < 0) {
  242. printf("no ethernet0 path offset\n");
  243. return -ENODEV;
  244. }
  245. ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
  246. if (ret) {
  247. printf("error setting mac-address property\n");
  248. return -ENODEV;
  249. }
  250. /* setup MAC2 */
  251. mac_addr[0] = header.MAC2[0];
  252. mac_addr[1] = header.MAC2[1];
  253. mac_addr[2] = header.MAC2[2];
  254. mac_addr[3] = header.MAC2[3];
  255. mac_addr[4] = header.MAC2[4];
  256. mac_addr[5] = header.MAC2[5];
  257. node = fdt_path_offset(blob, "ethernet1");
  258. if (node < 0) {
  259. printf("no ethernet1 path offset\n");
  260. return -ENODEV;
  261. }
  262. ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
  263. if (ret) {
  264. printf("error setting mac-address property\n");
  265. return -ENODEV;
  266. }
  267. printf("\nFDT was successfully setup\n");
  268. return 0;
  269. }
  270. static struct module_pin_mux pcie_sw_pin_mux[] = {
  271. {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
  272. {-1},
  273. };
  274. static struct module_pin_mux dip_pin_mux[] = {
  275. {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
  276. {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
  277. {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
  278. {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
  279. {-1},
  280. };
  281. #ifdef CONFIG_BOARD_LATE_INIT
  282. int board_late_init(void)
  283. {
  284. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  285. BSP_VS_HWPARAM header;
  286. char model[4];
  287. /* get production data */
  288. if (read_eeprom(&header)) {
  289. strcpy(model, "211");
  290. } else {
  291. sprintf(model, "%d", header.SystemId);
  292. if (header.SystemId == 215) {
  293. configure_module_pin_mux(dip_pin_mux);
  294. baltos_set_console();
  295. }
  296. }
  297. /* turn power for the mPCIe slot */
  298. configure_module_pin_mux(pcie_sw_pin_mux);
  299. if (gpio_request(MPCIE_SW, "mpcie_sw")) {
  300. printf("failed to export GPIO %d\n", MPCIE_SW);
  301. return -ENODEV;
  302. }
  303. if (gpio_direction_output(MPCIE_SW, 1)) {
  304. printf("failed to set GPIO %d direction\n", MPCIE_SW);
  305. return -ENODEV;
  306. }
  307. env_set("board_name", model);
  308. #endif
  309. return 0;
  310. }
  311. #endif
  312. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  313. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  314. static void cpsw_control(int enabled)
  315. {
  316. /* VTP can be added here */
  317. return;
  318. }
  319. static struct cpsw_slave_data cpsw_slaves[] = {
  320. {
  321. .slave_reg_ofs = 0x208,
  322. .sliver_reg_ofs = 0xd80,
  323. .phy_addr = 0,
  324. },
  325. {
  326. .slave_reg_ofs = 0x308,
  327. .sliver_reg_ofs = 0xdc0,
  328. .phy_addr = 7,
  329. },
  330. };
  331. static struct cpsw_platform_data cpsw_data = {
  332. .mdio_base = CPSW_MDIO_BASE,
  333. .cpsw_base = CPSW_BASE,
  334. .mdio_div = 0xff,
  335. .channels = 8,
  336. .cpdma_reg_ofs = 0x800,
  337. .slaves = 2,
  338. .slave_data = cpsw_slaves,
  339. .active_slave = 1,
  340. .ale_reg_ofs = 0xd00,
  341. .ale_entries = 1024,
  342. .host_port_reg_ofs = 0x108,
  343. .hw_stats_reg_ofs = 0x900,
  344. .bd_ram_ofs = 0x2000,
  345. .mac_control = (1 << 5),
  346. .control = cpsw_control,
  347. .host_port_num = 0,
  348. .version = CPSW_CTRL_VERSION_2,
  349. };
  350. #endif
  351. #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
  352. && defined(CONFIG_SPL_BUILD)) || \
  353. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  354. defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
  355. !defined(CONFIG_SPL_BUILD))
  356. int board_eth_init(struct bd_info *bis)
  357. {
  358. int rv, n = 0;
  359. uint8_t mac_addr[6];
  360. uint32_t mac_hi, mac_lo;
  361. /*
  362. * Note here that we're using CPSW1 since that has a 1Gbit PHY while
  363. * CSPW0 has a 100Mbit PHY.
  364. *
  365. * On product, CPSW1 maps to port labeled WAN.
  366. */
  367. /* try reading mac address from efuse */
  368. mac_lo = readl(&cdev->macid1l);
  369. mac_hi = readl(&cdev->macid1h);
  370. mac_addr[0] = mac_hi & 0xFF;
  371. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  372. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  373. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  374. mac_addr[4] = mac_lo & 0xFF;
  375. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  376. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  377. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  378. if (!env_get("ethaddr")) {
  379. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  380. if (is_valid_ethaddr(mac_addr))
  381. eth_env_set_enetaddr("ethaddr", mac_addr);
  382. }
  383. #ifdef CONFIG_DRIVER_TI_CPSW
  384. writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
  385. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
  386. rv = cpsw_register(&cpsw_data);
  387. if (rv < 0)
  388. printf("Error %d registering CPSW switch\n", rv);
  389. else
  390. n += rv;
  391. #endif
  392. /*
  393. *
  394. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  395. * operating points. So we must set the TX clock delay feature
  396. * in the AR8051 PHY. Since we only support a single ethernet
  397. * device in U-Boot, we only do this for the first instance.
  398. */
  399. #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
  400. #define AR8051_PHY_DEBUG_DATA_REG 0x1e
  401. #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
  402. #define AR8051_RGMII_TX_CLK_DLY 0x100
  403. const char *devname;
  404. devname = miiphy_get_current_dev();
  405. miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
  406. AR8051_DEBUG_RGMII_CLK_DLY_REG);
  407. miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
  408. AR8051_RGMII_TX_CLK_DLY);
  409. #endif
  410. return n;
  411. }
  412. #endif