ve8313.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
  4. *
  5. * Author: Scott Wood <scottwood@freescale.com>
  6. *
  7. * (C) Copyright 2010
  8. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  9. */
  10. #include <common.h>
  11. #include <fdt_support.h>
  12. #include <init.h>
  13. #include <linux/delay.h>
  14. #include <linux/libfdt.h>
  15. #include <pci.h>
  16. #include <mpc83xx.h>
  17. #include <ns16550.h>
  18. #include <nand.h>
  19. #include <asm/bitops.h>
  20. #include <asm/io.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. extern void disable_addr_trans (void);
  23. extern void enable_addr_trans (void);
  24. int checkboard(void)
  25. {
  26. puts("Board: ve8313\n");
  27. return 0;
  28. }
  29. static long fixed_sdram(void)
  30. {
  31. u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  32. #ifndef CONFIG_SYS_RAMBOOT
  33. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  34. u32 msize_log2 = __ilog2(msize);
  35. out_be32(&im->sysconf.ddrlaw[0].bar,
  36. (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
  37. out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
  38. out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
  39. /*
  40. * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  41. * or the DDR2 controller may fail to initialize correctly.
  42. */
  43. __udelay(50000);
  44. #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  45. #warning Chip select bounds is only configurable in 16MB increments
  46. #endif
  47. out_be32(&im->ddr.csbnds[0].csbnds,
  48. ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  49. (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
  50. CSBNDS_EA));
  51. out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
  52. /* Currently we use only one CS, so disable the other bank. */
  53. out_be32(&im->ddr.cs_config[1], 0);
  54. out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
  55. out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  56. out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  57. out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  58. out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  59. out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
  60. out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
  61. out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  62. out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
  63. out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  64. sync();
  65. /* enable DDR controller */
  66. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  67. /* now check the real size */
  68. disable_addr_trans ();
  69. msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
  70. enable_addr_trans ();
  71. #endif
  72. return msize;
  73. }
  74. int dram_init(void)
  75. {
  76. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  77. volatile fsl_lbc_t *lbc = &im->im_lbc;
  78. u32 msize;
  79. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  80. return -1;
  81. /* DDR SDRAM - Main SODIMM */
  82. msize = fixed_sdram();
  83. /* Local Bus setup lbcr and mrtpr */
  84. out_be32(&lbc->lbcr, 0x00040000);
  85. out_be32(&lbc->mrtpr, 0x20000000);
  86. sync();
  87. /* return total bus SDRAM size(bytes) -- DDR */
  88. gd->ram_size = msize;
  89. return 0;
  90. }
  91. #define VE8313_WDT_EN 0x00020000
  92. #define VE8313_WDT_TRIG 0x00040000
  93. int board_early_init_f (void)
  94. {
  95. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  96. volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
  97. #if defined(CONFIG_HW_WATCHDOG)
  98. /* enable WDT */
  99. clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
  100. #else
  101. /* disable WDT */
  102. setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
  103. #endif
  104. /* set WDT pins as output */
  105. setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
  106. return 0;
  107. }
  108. #if defined(CONFIG_HW_WATCHDOG)
  109. void hw_watchdog_reset(void)
  110. {
  111. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  112. volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
  113. unsigned long reg;
  114. reg = in_be32(&gpio->dat);
  115. if (reg & VE8313_WDT_TRIG)
  116. clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
  117. else
  118. setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
  119. }
  120. #endif
  121. #if defined(CONFIG_PCI)
  122. static struct pci_region pci_regions[] = {
  123. {
  124. bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  125. phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  126. size: CONFIG_SYS_PCI1_MEM_SIZE,
  127. flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  128. },
  129. {
  130. bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  131. phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  132. size: CONFIG_SYS_PCI1_MMIO_SIZE,
  133. flags: PCI_REGION_MEM
  134. },
  135. {
  136. bus_start: CONFIG_SYS_PCI1_IO_BASE,
  137. phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  138. size: CONFIG_SYS_PCI1_IO_SIZE,
  139. flags: PCI_REGION_IO
  140. }
  141. };
  142. void pci_init_board(void)
  143. {
  144. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  145. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  146. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  147. struct pci_region *reg[] = { pci_regions };
  148. /* Enable all 3 PCI_CLK_OUTPUTs. */
  149. setbits_be32(&clk->occr, 0xe0000000);
  150. /*
  151. * Configure PCI Local Access Windows
  152. */
  153. out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
  154. out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  155. out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
  156. out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
  157. mpc83xx_pci_init(1, reg);
  158. }
  159. #endif
  160. #if defined(CONFIG_OF_BOARD_SETUP)
  161. int ft_board_setup(void *blob, struct bd_info *bd)
  162. {
  163. ft_cpu_setup(blob, bd);
  164. #ifdef CONFIG_PCI
  165. ft_pci_setup(blob, bd);
  166. #endif
  167. return 0;
  168. }
  169. #endif