tlb.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Author: Adrian Cox
  4. * Based on corenet_ds tlb code
  5. */
  6. #include <common.h>
  7. #include <asm/mmu.h>
  8. struct fsl_e_tlb_entry tlb_table[] = {
  9. /* TLB 0 - for temp stack in cache */
  10. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  11. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  12. MAS3_SW|MAS3_SR, 0,
  13. 0, 0, BOOKE_PAGESZ_4K, 0),
  14. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  15. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  16. MAS3_SW|MAS3_SR, 0,
  17. 0, 0, BOOKE_PAGESZ_4K, 0),
  18. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  19. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  20. MAS3_SW|MAS3_SR, 0,
  21. 0, 0, BOOKE_PAGESZ_4K, 0),
  22. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  23. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  24. MAS3_SW|MAS3_SR, 0,
  25. 0, 0, BOOKE_PAGESZ_4K, 0),
  26. /* TLB 1 */
  27. /* *I*** - Covers boot page */
  28. #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  29. /*
  30. * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  31. * SRAM is at 0xfff00000, it covered the 0xfffff000.
  32. */
  33. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  34. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  35. 0, 0, BOOKE_PAGESZ_1M, 1),
  36. #else
  37. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  38. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  39. 0, 0, BOOKE_PAGESZ_4K, 1),
  40. #endif
  41. /* *I*G* - CCSRBAR */
  42. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  43. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  44. 0, 1, BOOKE_PAGESZ_16M, 1),
  45. /* Local Bus */
  46. SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS,
  47. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  48. 0, 2, BOOKE_PAGESZ_64K, 1),
  49. SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS,
  50. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  51. 0, 3, BOOKE_PAGESZ_4K, 1),
  52. /* *I*G* - PCI */
  53. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  54. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  55. 0, 4, BOOKE_PAGESZ_1G, 1),
  56. /* *I*G* - PCI */
  57. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  58. CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  59. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60. 0, 5, BOOKE_PAGESZ_256M, 1),
  61. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  62. CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  63. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  64. 0, 6, BOOKE_PAGESZ_256M, 1),
  65. /* *I*G* - PCI I/O */
  66. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  67. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68. 0, 7, BOOKE_PAGESZ_256K, 1),
  69. /* Bman/Qman */
  70. #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  71. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  72. MAS3_SW|MAS3_SR, 0,
  73. 0, 9, BOOKE_PAGESZ_1M, 1),
  74. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
  75. CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
  76. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  77. 0, 10, BOOKE_PAGESZ_1M, 1),
  78. #endif
  79. #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  80. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  81. MAS3_SW|MAS3_SR, 0,
  82. 0, 11, BOOKE_PAGESZ_1M, 1),
  83. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
  84. CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
  85. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  86. 0, 12, BOOKE_PAGESZ_1M, 1),
  87. #endif
  88. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  89. SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  90. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  91. 0, 13, BOOKE_PAGESZ_4M, 1),
  92. #endif
  93. };
  94. int num_tlb_entries = ARRAY_SIZE(tlb_table);