eth.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Author Adrian Cox
  4. * Based somewhat on board/freescale/corenet_ds/eth_hydra.c
  5. */
  6. #include <common.h>
  7. #include <net.h>
  8. #include <netdev.h>
  9. #include <asm/fsl_serdes.h>
  10. #include <fm_eth.h>
  11. #include <fsl_mdio.h>
  12. #include <malloc.h>
  13. #include <fdt_support.h>
  14. #include <fsl_dtsec.h>
  15. #ifdef CONFIG_FMAN_ENET
  16. #define FIRST_PORT_ADDR 3
  17. #define SECOND_PORT_ADDR 7
  18. #ifdef CONFIG_ARCH_P5040
  19. #define FIRST_PORT FM1_DTSEC5
  20. #define SECOND_PORT FM2_DTSEC5
  21. #else
  22. #define FIRST_PORT FM1_DTSEC4
  23. #define SECOND_PORT FM1_DTSEC5
  24. #endif
  25. #define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT)
  26. static void cyrus_phy_tuning(int phy)
  27. {
  28. /*
  29. * Enable RGMII delay on Tx and Rx for CPU port
  30. */
  31. printf("Tuning PHY @ %d\n", phy);
  32. /* sets address 0x104 or reg 260 for writing */
  33. miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104);
  34. /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */
  35. miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0);
  36. /* sets address 0x105 or reg 261 for writing */
  37. miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105);
  38. /* writes to address 0x105 , RXD[3..0] to -0. */
  39. miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
  40. /* sets address 0x106 or reg 261 for writing */
  41. miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106);
  42. /* writes to address 0x106 , TXD[3..0] to -0.84ns */
  43. miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
  44. /* force re-negotiation */
  45. miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340);
  46. }
  47. #endif
  48. int board_eth_init(struct bd_info *bis)
  49. {
  50. #ifdef CONFIG_FMAN_ENET
  51. struct fsl_pq_mdio_info dtsec_mdio_info;
  52. unsigned int i;
  53. printf("Initializing Fman\n");
  54. /* Register the real 1G MDIO bus */
  55. dtsec_mdio_info.regs =
  56. (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
  57. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  58. fsl_pq_mdio_init(bis, &dtsec_mdio_info);
  59. fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR);
  60. fm_info_set_mdio(FIRST_PORT,
  61. miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
  62. fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR);
  63. fm_info_set_mdio(SECOND_PORT,
  64. miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
  65. /* Never disable DTSEC1 - it controls MDIO */
  66. for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  67. if (!IS_VALID_PORT(i))
  68. fm_disable_port(i);
  69. }
  70. #ifdef CONFIG_ARCH_P5040
  71. for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  72. if (!IS_VALID_PORT(i))
  73. fm_disable_port(i);
  74. }
  75. #endif
  76. cpu_eth_init(bis);
  77. cyrus_phy_tuning(FIRST_PORT_ADDR);
  78. cyrus_phy_tuning(SECOND_PORT_ADDR);
  79. #endif
  80. return pci_eth_init(bis);
  81. }