ddr.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Based on corenet_ds ddr code
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <hwconfig.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/mmu.h>
  11. #include <fsl_ddr_sdram.h>
  12. #include <fsl_ddr_dimm_params.h>
  13. #include <asm/fsl_law.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. struct board_specific_parameters {
  16. u32 n_ranks;
  17. u32 datarate_mhz_high;
  18. u32 clk_adjust;
  19. u32 wrlvl_start;
  20. u32 cpo;
  21. u32 write_data_delay;
  22. u32 force_2t;
  23. };
  24. /*
  25. * This table contains all valid speeds we want to override with board
  26. * specific parameters. datarate_mhz_high values need to be in ascending order
  27. * for each n_ranks group.
  28. */
  29. static const struct board_specific_parameters udimm0[] = {
  30. /*
  31. * memory controller 0
  32. * num| hi| clk| wrlvl | cpo |wrdata|2T
  33. * ranks| mhz|adjst| start | |delay |
  34. */
  35. {4, 850, 4, 6, 0xff, 2, 0},
  36. {4, 950, 5, 7, 0xff, 2, 0},
  37. {4, 1050, 5, 8, 0xff, 2, 0},
  38. {4, 1250, 5, 10, 0xff, 2, 0},
  39. {4, 1350, 5, 11, 0xff, 2, 0},
  40. {4, 1666, 5, 12, 0xff, 2, 0},
  41. {2, 850, 5, 6, 0xff, 2, 0},
  42. {2, 1050, 5, 7, 0xff, 2, 0},
  43. {2, 1250, 4, 6, 0xff, 2, 0},
  44. {2, 1350, 5, 7, 0xff, 2, 0},
  45. {2, 1666, 5, 8, 0xff, 2, 0},
  46. {1, 1250, 4, 6, 0xff, 2, 0},
  47. {1, 1335, 4, 7, 0xff, 2, 0},
  48. {1, 1666, 4, 8, 0xff, 2, 0},
  49. {}
  50. };
  51. /*
  52. * The two slots have slightly different timing. The center values are good
  53. * for both slots. We use identical speed tables for them. In future use, if
  54. * DIMMs have fewer center values that require two separated tables, copy the
  55. * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
  56. */
  57. static const struct board_specific_parameters *udimms[] = {
  58. udimm0,
  59. udimm0,
  60. };
  61. static const struct board_specific_parameters rdimm0[] = {
  62. /*
  63. * memory controller 0
  64. * num| hi| clk| wrlvl | cpo |wrdata|2T
  65. * ranks| mhz|adjst| start | |delay |
  66. */
  67. {4, 850, 4, 6, 0xff, 2, 0},
  68. {4, 950, 5, 7, 0xff, 2, 0},
  69. {4, 1050, 5, 8, 0xff, 2, 0},
  70. {4, 1250, 5, 10, 0xff, 2, 0},
  71. {4, 1350, 5, 11, 0xff, 2, 0},
  72. {4, 1666, 5, 12, 0xff, 2, 0},
  73. {2, 850, 4, 6, 0xff, 2, 0},
  74. {2, 1050, 4, 7, 0xff, 2, 0},
  75. {2, 1666, 4, 8, 0xff, 2, 0},
  76. {1, 850, 4, 5, 0xff, 2, 0},
  77. {1, 950, 4, 7, 0xff, 2, 0},
  78. {1, 1666, 4, 8, 0xff, 2, 0},
  79. {}
  80. };
  81. /*
  82. * The two slots have slightly different timing. See comments above.
  83. */
  84. static const struct board_specific_parameters *rdimms[] = {
  85. rdimm0,
  86. rdimm0,
  87. };
  88. void fsl_ddr_board_options(memctl_options_t *popts,
  89. dimm_params_t *pdimm,
  90. unsigned int ctrl_num)
  91. {
  92. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  93. ulong ddr_freq;
  94. if (ctrl_num > 1) {
  95. printf("Wrong parameter for controller number %d", ctrl_num);
  96. return;
  97. }
  98. if (!pdimm->n_ranks)
  99. return;
  100. if (popts->registered_dimm_en)
  101. pbsp = rdimms[ctrl_num];
  102. else
  103. pbsp = udimms[ctrl_num];
  104. /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  105. * freqency and n_banks specified in board_specific_parameters table.
  106. */
  107. ddr_freq = get_ddr_freq(0) / 1000000;
  108. while (pbsp->datarate_mhz_high) {
  109. if (pbsp->n_ranks == pdimm->n_ranks) {
  110. if (ddr_freq <= pbsp->datarate_mhz_high) {
  111. popts->cpo_override = pbsp->cpo;
  112. popts->write_data_delay =
  113. pbsp->write_data_delay;
  114. popts->clk_adjust = pbsp->clk_adjust;
  115. popts->wrlvl_start = pbsp->wrlvl_start;
  116. popts->twot_en = pbsp->force_2t;
  117. goto found;
  118. }
  119. pbsp_highest = pbsp;
  120. }
  121. pbsp++;
  122. }
  123. if (pbsp_highest) {
  124. printf("Error: board specific timing not found for data rate %lu MT/s!\nTrying to use the highest speed (%u) parameters\n",
  125. ddr_freq, pbsp_highest->datarate_mhz_high);
  126. popts->cpo_override = pbsp_highest->cpo;
  127. popts->write_data_delay = pbsp_highest->write_data_delay;
  128. popts->clk_adjust = pbsp_highest->clk_adjust;
  129. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  130. popts->twot_en = pbsp_highest->force_2t;
  131. } else {
  132. panic("DIMM is not supported by this board");
  133. }
  134. found:
  135. /*
  136. * Factors to consider for half-strength driver enable:
  137. * - number of DIMMs installed
  138. */
  139. popts->half_strength_driver_enable = 0;
  140. /*
  141. * Write leveling override
  142. */
  143. popts->wrlvl_override = 1;
  144. popts->wrlvl_sample = 0xf;
  145. /*
  146. * Rtt and Rtt_WR override
  147. */
  148. popts->rtt_override = 0;
  149. /* Enable ZQ calibration */
  150. popts->zq_en = 1;
  151. /* DHC_EN =1, ODT = 60 Ohm */
  152. popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
  153. }
  154. int dram_init(void)
  155. {
  156. phys_size_t dram_size;
  157. puts("Initializing....");
  158. if (!fsl_use_spd())
  159. panic("Cyrus only supports using SPD for DRAM\n");
  160. puts("using SPD\n");
  161. dram_size = fsl_ddr_sdram();
  162. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  163. dram_size *= 0x100000;
  164. debug(" DDR: ");
  165. gd->ram_size = dram_size;
  166. return 0;
  167. }