udoo_spl.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Udoo
  4. * Author: Tungyi Lin <tungyilin1127@gmail.com>
  5. * Richard Hu <hakahu@gmail.com>
  6. * Based on board/wandboard/spl.c
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/iomux.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <linux/delay.h>
  15. #include <linux/errno.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/video.h>
  19. #include <mmc.h>
  20. #include <fsl_esdhc_imx.h>
  21. #include <asm/arch/crm_regs.h>
  22. #include <asm/io.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <spl.h>
  25. #if defined(CONFIG_SPL_BUILD)
  26. #include <asm/arch/mx6-ddr.h>
  27. /*
  28. * Driving strength:
  29. * 0x30 == 40 Ohm
  30. * 0x28 == 48 Ohm
  31. */
  32. #define IMX6DQ_DRIVE_STRENGTH 0x30
  33. #define IMX6SDL_DRIVE_STRENGTH 0x28
  34. /* configure MX6Q/DUAL mmdc DDR io registers */
  35. static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  36. .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
  37. .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
  38. .dram_cas = IMX6DQ_DRIVE_STRENGTH,
  39. .dram_ras = IMX6DQ_DRIVE_STRENGTH,
  40. .dram_reset = IMX6DQ_DRIVE_STRENGTH,
  41. .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
  42. .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
  43. .dram_sdba2 = 0x00000000,
  44. .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
  45. .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
  46. .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
  47. .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
  48. .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
  49. .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
  50. .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
  51. .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
  52. .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
  53. .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
  54. .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
  55. .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
  56. .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
  57. .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
  58. .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
  59. .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
  60. .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
  61. .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
  62. };
  63. /* configure MX6Q/DUAL mmdc GRP io registers */
  64. static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  65. .grp_ddr_type = 0x000c0000,
  66. .grp_ddrmode_ctl = 0x00020000,
  67. .grp_ddrpke = 0x00000000,
  68. .grp_addds = IMX6DQ_DRIVE_STRENGTH,
  69. .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
  70. .grp_ddrmode = 0x00020000,
  71. .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
  72. .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
  73. .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
  74. .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
  75. .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
  76. .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
  77. .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
  78. .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
  79. };
  80. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  81. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  82. .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  83. .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  84. .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  85. .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  86. .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  87. .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  88. .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  89. .dram_sdba2 = 0x00000000,
  90. .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  91. .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  92. .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  93. .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  94. .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  95. .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  96. .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  97. .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  98. .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  99. .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  100. .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  101. .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  102. .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  103. .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  104. .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  105. .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  106. .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  107. .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  108. };
  109. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  110. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  111. .grp_ddr_type = 0x000c0000,
  112. .grp_ddrmode_ctl = 0x00020000,
  113. .grp_ddrpke = 0x00000000,
  114. .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  115. .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  116. .grp_ddrmode = 0x00020000,
  117. .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  118. .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  119. .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  120. .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  121. .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  122. .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  123. .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  124. .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  125. };
  126. /* MT41K128M16JT-125 */
  127. static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  128. /* quad = 1066, duallite = 800 */
  129. .mem_speed = 1066,
  130. .density = 2,
  131. .width = 16,
  132. .banks = 8,
  133. .rowaddr = 14,
  134. .coladdr = 10,
  135. .pagesz = 2,
  136. .trcd = 1375,
  137. .trcmin = 4875,
  138. .trasmin = 3500,
  139. .SRT = 0,
  140. };
  141. static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
  142. .p0_mpwldectrl0 = 0x00350035,
  143. .p0_mpwldectrl1 = 0x001F001F,
  144. .p1_mpwldectrl0 = 0x00010001,
  145. .p1_mpwldectrl1 = 0x00010001,
  146. .p0_mpdgctrl0 = 0x43510360,
  147. .p0_mpdgctrl1 = 0x0342033F,
  148. .p1_mpdgctrl0 = 0x033F033F,
  149. .p1_mpdgctrl1 = 0x03290266,
  150. .p0_mprddlctl = 0x4B3E4141,
  151. .p1_mprddlctl = 0x47413B4A,
  152. .p0_mpwrdlctl = 0x42404843,
  153. .p1_mpwrdlctl = 0x4C3F4C45,
  154. };
  155. static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
  156. .p0_mpwldectrl0 = 0x002F0038,
  157. .p0_mpwldectrl1 = 0x001F001F,
  158. .p1_mpwldectrl0 = 0x001F001F,
  159. .p1_mpwldectrl1 = 0x001F001F,
  160. .p0_mpdgctrl0 = 0x425C0251,
  161. .p0_mpdgctrl1 = 0x021B021E,
  162. .p1_mpdgctrl0 = 0x021B021E,
  163. .p1_mpdgctrl1 = 0x01730200,
  164. .p0_mprddlctl = 0x45474C45,
  165. .p1_mprddlctl = 0x44464744,
  166. .p0_mpwrdlctl = 0x3F3F3336,
  167. .p1_mpwrdlctl = 0x32383630,
  168. };
  169. /* DDR 64bit 1GB */
  170. static struct mx6_ddr_sysinfo mem_qdl = {
  171. .dsize = 2,
  172. .cs1_mirror = 0,
  173. /* config for full 4GB range so that get_mem_size() works */
  174. .cs_density = 32,
  175. .ncs = 1,
  176. .bi_on = 1,
  177. /* quad = 2, duallite = 1 */
  178. .rtt_nom = 2,
  179. /* quad = 2, duallite = 1 */
  180. .rtt_wr = 2,
  181. .ralat = 5,
  182. .walat = 0,
  183. .mif3_mode = 3,
  184. .rst_to_cke = 0x23,
  185. .sde_to_rst = 0x10,
  186. .refsel = 1, /* Refresh cycles at 32KHz */
  187. .refr = 7, /* 8 refresh commands per refresh cycle */
  188. };
  189. static void ccgr_init(void)
  190. {
  191. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  192. /* set the default clock gate to save power */
  193. writel(0x00C03F3F, &ccm->CCGR0);
  194. writel(0x0030FC03, &ccm->CCGR1);
  195. writel(0x0FFFC000, &ccm->CCGR2);
  196. writel(0x3FF00000, &ccm->CCGR3);
  197. writel(0x00FFF300, &ccm->CCGR4);
  198. writel(0x0F0000C3, &ccm->CCGR5);
  199. writel(0x000003FF, &ccm->CCGR6);
  200. }
  201. static void spl_dram_init(void)
  202. {
  203. if (is_cpu_type(MXC_CPU_MX6DL)) {
  204. mt41k128m16jt_125.mem_speed = 800;
  205. mem_qdl.rtt_nom = 1;
  206. mem_qdl.rtt_wr = 1;
  207. mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  208. mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
  209. } else if (is_cpu_type(MXC_CPU_MX6Q)) {
  210. mt41k128m16jt_125.mem_speed = 1066;
  211. mem_qdl.rtt_nom = 2;
  212. mem_qdl.rtt_wr = 2;
  213. mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
  214. mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125);
  215. }
  216. udelay(100);
  217. }
  218. void board_init_f(ulong dummy)
  219. {
  220. ccgr_init();
  221. /* setup AIPS and disable watchdog */
  222. arch_cpu_init();
  223. gpr_init();
  224. /* iomux */
  225. board_early_init_f();
  226. /* setup GP timer */
  227. timer_init();
  228. /* UART clocks enabled and gd valid - init serial console */
  229. preloader_console_init();
  230. /* DDR initialization */
  231. spl_dram_init();
  232. }
  233. #endif