udoo.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <env.h>
  13. #include <malloc.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <asm/gpio.h>
  18. #include <asm/mach-imx/iomux-v3.h>
  19. #include <asm/mach-imx/sata.h>
  20. #include <mmc.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <asm/arch/crm_regs.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <micrel.h>
  26. #include <miiphy.h>
  27. #include <netdev.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  30. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  31. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  32. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  33. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  34. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  35. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  36. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define WDT_EN IMX_GPIO_NR(5, 4)
  38. #define WDT_TRG IMX_GPIO_NR(3, 19)
  39. int dram_init(void)
  40. {
  41. gd->ram_size = imx_ddr_size();
  42. return 0;
  43. }
  44. static iomux_v3_cfg_t const uart2_pads[] = {
  45. IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  46. IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  47. };
  48. static iomux_v3_cfg_t const usdhc3_pads[] = {
  49. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  50. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  51. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  52. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  53. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  54. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  55. };
  56. static iomux_v3_cfg_t const wdog_pads[] = {
  57. IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  58. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
  59. };
  60. int mx6_rgmii_rework(struct phy_device *phydev)
  61. {
  62. /*
  63. * Bug: Apparently uDoo does not works with Gigabit switches...
  64. * Limiting speed to 10/100Mbps, and setting master mode, seems to
  65. * be the only way to have a successfull PHY auto negotiation.
  66. * How to fix: Understand why Linux kernel do not have this issue.
  67. */
  68. phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
  69. /* control data pad skew - devaddr = 0x02, register = 0x04 */
  70. ksz9031_phy_extended_write(phydev, 0x02,
  71. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  72. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  73. /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  74. ksz9031_phy_extended_write(phydev, 0x02,
  75. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  76. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  77. /* tx data pad skew - devaddr = 0x02, register = 0x05 */
  78. ksz9031_phy_extended_write(phydev, 0x02,
  79. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  80. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  81. /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  82. ksz9031_phy_extended_write(phydev, 0x02,
  83. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  84. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  85. return 0;
  86. }
  87. static iomux_v3_cfg_t const enet_pads1[] = {
  88. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  90. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  91. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  92. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  93. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  94. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  95. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  96. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  97. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  98. /* RGMII reset */
  99. IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  100. /* Ethernet power supply */
  101. IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  102. /* pin 32 - 1 - (MODE0) all */
  103. IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  104. /* pin 31 - 1 - (MODE1) all */
  105. IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  106. /* pin 28 - 1 - (MODE2) all */
  107. IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  108. /* pin 27 - 1 - (MODE3) all */
  109. IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  110. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  111. IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  112. };
  113. static iomux_v3_cfg_t const enet_pads2[] = {
  114. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  115. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  116. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  117. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  118. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  119. };
  120. static void setup_iomux_enet(void)
  121. {
  122. SETUP_IOMUX_PADS(enet_pads1);
  123. udelay(20);
  124. gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
  125. gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
  126. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  127. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  128. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  129. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  130. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  131. udelay(1000);
  132. gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
  133. /* Need 100ms delay to exit from reset. */
  134. udelay(1000 * 100);
  135. gpio_free(IMX_GPIO_NR(6, 24));
  136. gpio_free(IMX_GPIO_NR(6, 25));
  137. gpio_free(IMX_GPIO_NR(6, 27));
  138. gpio_free(IMX_GPIO_NR(6, 28));
  139. gpio_free(IMX_GPIO_NR(6, 29));
  140. SETUP_IOMUX_PADS(enet_pads2);
  141. }
  142. static void setup_iomux_uart(void)
  143. {
  144. SETUP_IOMUX_PADS(uart2_pads);
  145. }
  146. static void setup_iomux_wdog(void)
  147. {
  148. SETUP_IOMUX_PADS(wdog_pads);
  149. gpio_direction_output(WDT_TRG, 0);
  150. gpio_direction_output(WDT_EN, 1);
  151. gpio_direction_input(WDT_TRG);
  152. }
  153. static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
  154. int board_mmc_getcd(struct mmc *mmc)
  155. {
  156. return 1; /* Always present */
  157. }
  158. int board_eth_init(struct bd_info *bis)
  159. {
  160. uint32_t base = IMX_FEC_BASE;
  161. struct mii_dev *bus = NULL;
  162. struct phy_device *phydev = NULL;
  163. int ret;
  164. setup_iomux_enet();
  165. #ifdef CONFIG_FEC_MXC
  166. bus = fec_get_miibus(base, -1);
  167. if (!bus)
  168. return -EINVAL;
  169. /* scan phy 4,5,6,7 */
  170. phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  171. if (!phydev) {
  172. ret = -EINVAL;
  173. goto free_bus;
  174. }
  175. printf("using phy at %d\n", phydev->addr);
  176. ret = fec_probe(bis, -1, base, bus, phydev);
  177. if (ret)
  178. goto free_phydev;
  179. #endif
  180. return 0;
  181. free_phydev:
  182. free(phydev);
  183. free_bus:
  184. free(bus);
  185. return ret;
  186. }
  187. int board_mmc_init(struct bd_info *bis)
  188. {
  189. SETUP_IOMUX_PADS(usdhc3_pads);
  190. usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  191. usdhc_cfg.max_bus_width = 4;
  192. return fsl_esdhc_initialize(bis, &usdhc_cfg);
  193. }
  194. int board_early_init_f(void)
  195. {
  196. setup_iomux_wdog();
  197. setup_iomux_uart();
  198. return 0;
  199. }
  200. int board_phy_config(struct phy_device *phydev)
  201. {
  202. mx6_rgmii_rework(phydev);
  203. if (phydev->drv->config)
  204. phydev->drv->config(phydev);
  205. return 0;
  206. }
  207. int board_init(void)
  208. {
  209. /* address of boot parameters */
  210. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  211. #ifdef CONFIG_SATA
  212. setup_sata();
  213. #endif
  214. return 0;
  215. }
  216. int board_late_init(void)
  217. {
  218. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  219. if (is_cpu_type(MXC_CPU_MX6Q))
  220. env_set("board_rev", "MX6Q");
  221. else
  222. env_set("board_rev", "MX6DL");
  223. #endif
  224. return 0;
  225. }
  226. int checkboard(void)
  227. {
  228. if (is_cpu_type(MXC_CPU_MX6Q))
  229. puts("Board: Udoo Quad\n");
  230. else
  231. puts("Board: Udoo DualLite\n");
  232. return 0;
  233. }