spl.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2020 Toradex
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <image.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/ddr.h>
  12. #include <asm/arch/imx8mm_pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/io.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <cpu_func.h>
  18. #include <dm/device.h>
  19. #include <dm/device-internal.h>
  20. #include <dm/uclass.h>
  21. #include <dm/uclass-internal.h>
  22. #include <hang.h>
  23. #include <i2c.h>
  24. #include <power/bd71837.h>
  25. #include <power/pca9450.h>
  26. #include <power/pmic.h>
  27. #include <spl.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define I2C_PMIC_BUS_ID 1
  30. int spl_board_boot_device(enum boot_device boot_dev_spl)
  31. {
  32. switch (boot_dev_spl) {
  33. case MMC1_BOOT:
  34. return BOOT_DEVICE_MMC1;
  35. case SD2_BOOT:
  36. case MMC2_BOOT:
  37. return BOOT_DEVICE_MMC2;
  38. case SD3_BOOT:
  39. case MMC3_BOOT:
  40. return BOOT_DEVICE_MMC1;
  41. case USB_BOOT:
  42. return BOOT_DEVICE_BOARD;
  43. default:
  44. return BOOT_DEVICE_NONE;
  45. }
  46. }
  47. void spl_dram_init(void)
  48. {
  49. ddr_init(&dram_timing);
  50. }
  51. void spl_board_init(void)
  52. {
  53. /* Serial download mode */
  54. if (is_usb_boot()) {
  55. puts("Back to ROM, SDP\n");
  56. restore_boot_params();
  57. }
  58. puts("Normal Boot\n");
  59. }
  60. #ifdef CONFIG_SPL_LOAD_FIT
  61. int board_fit_config_name_match(const char *name)
  62. {
  63. /* Just empty function now - can't decide what to choose */
  64. debug("%s: %s\n", __func__, name);
  65. return 0;
  66. }
  67. #endif
  68. #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
  69. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  70. /* Verdin UART_3, Console/Debug UART */
  71. static iomux_v3_cfg_t const uart_pads[] = {
  72. IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  73. IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  74. };
  75. static iomux_v3_cfg_t const wdog_pads[] = {
  76. IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  77. };
  78. int board_early_init_f(void)
  79. {
  80. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  81. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  82. set_wdog_reset(wdog);
  83. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  84. return 0;
  85. }
  86. int power_init_board(void)
  87. {
  88. struct udevice *dev;
  89. int ret;
  90. if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
  91. ret = pmic_get("pmic", &dev);
  92. if (ret == -ENODEV) {
  93. puts("No pmic found\n");
  94. return ret;
  95. }
  96. if (ret != 0)
  97. return ret;
  98. /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
  99. pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
  100. /* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */
  101. pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
  102. /* set WDOG_B_CFG to cold reset */
  103. pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
  104. pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
  105. return 0;
  106. }
  107. return 0;
  108. }
  109. void board_init_f(ulong dummy)
  110. {
  111. struct udevice *dev;
  112. int ret;
  113. arch_cpu_init();
  114. init_uart_clk(0);
  115. board_early_init_f();
  116. timer_init();
  117. preloader_console_init();
  118. /* Clear the BSS. */
  119. memset(__bss_start, 0, __bss_end - __bss_start);
  120. ret = spl_early_init();
  121. if (ret) {
  122. debug("spl_early_init() failed: %d\n", ret);
  123. hang();
  124. }
  125. ret = uclass_get_device_by_name(UCLASS_CLK,
  126. "clock-controller@30380000",
  127. &dev);
  128. if (ret < 0) {
  129. printf("Failed to find clock node. Check device tree\n");
  130. hang();
  131. }
  132. enable_tzc380();
  133. power_init_board();
  134. /* DDR initialization */
  135. spl_dram_init();
  136. board_init_r(NULL, 0);
  137. }