colibri_vf.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015-2019 Toradex, Inc.
  4. *
  5. * Based on vf610twr.c:
  6. * Copyright 2013 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/crm_regs.h>
  12. #include <asm/arch/ddrmc-vf610.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/iomux-vf610.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <env.h>
  18. #include <fdt_support.h>
  19. #include <fsl_dcu_fb.h>
  20. #include <g_dnl.h>
  21. #include <jffs2/load_kernel.h>
  22. #include <mtd_node.h>
  23. #include <usb.h>
  24. #include "../common/tdx-common.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define PTC0_GPIO_45 45
  27. static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
  28. { DDRMC_CR79_CTLUPD_AREF(1), 79 },
  29. /* sets manual values for read lvl. (gate) delay of data slice 0/1 */
  30. { DDRMC_CR105_RDLVL_DL_0(28), 105 },
  31. { DDRMC_CR106_RDLVL_GTDL_0(24), 106 },
  32. { DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 },
  33. { DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 },
  34. /* AXI */
  35. { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
  36. { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  37. { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  38. DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  39. { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  40. DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  41. { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  42. DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  43. { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  44. DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  45. { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  46. { DDRMC_CR126_PHY_RDLAT(8), 126 },
  47. { DDRMC_CR132_WRLAT_ADJ(5) |
  48. DDRMC_CR132_RDLAT_ADJ(6), 132 },
  49. { DDRMC_CR137_PHYCTL_DL(2), 137 },
  50. { DDRMC_CR138_PHY_WRLV_MXDL(256) |
  51. DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
  52. { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  53. DDRMC_CR139_PHY_WRLV_DLL(3) |
  54. DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  55. { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
  56. { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
  57. DDRMC_CR143_RDLV_MXDL(128), 143 },
  58. { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
  59. DDRMC_CR144_PHY_RDLV_DLL(3) |
  60. DDRMC_CR144_PHY_RDLV_EN(3), 144 },
  61. { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
  62. { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
  63. { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
  64. { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
  65. { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
  66. DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
  67. { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  68. DDRMC_CR154_PAD_ZQ_MODE(1) |
  69. DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  70. DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
  71. { DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
  72. { DDRMC_CR158_TWR(6), 158 },
  73. { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
  74. DDRMC_CR161_TODTH_WR(2), 161 },
  75. /* end marker */
  76. { 0, -1 }
  77. };
  78. int dram_init(void)
  79. {
  80. static const struct ddr3_jedec_timings timings = {
  81. .tinit = 5,
  82. .trst_pwron = 80000,
  83. .cke_inactive = 200000,
  84. .wrlat = 5,
  85. .caslat_lin = 12,
  86. .trc = 21,
  87. .trrd = 4,
  88. .tccd = 4,
  89. .tbst_int_interval = 0,
  90. .tfaw = 20,
  91. .trp = 6,
  92. .twtr = 4,
  93. .tras_min = 15,
  94. .tmrd = 4,
  95. .trtp = 4,
  96. .tras_max = 28080,
  97. .tmod = 12,
  98. .tckesr = 4,
  99. .tcke = 3,
  100. .trcd_int = 6,
  101. .tras_lockout = 0,
  102. .tdal = 12,
  103. .bstlen = 3,
  104. .tdll = 512, /* not applicable since freq. scaling
  105. * is not used
  106. */
  107. .trp_ab = 6,
  108. .tref = 3120,
  109. .trfc = 64,
  110. .tref_int = 0,
  111. .tpdex = 3,
  112. .txpdll = 10,
  113. .txsnr = 68, /* changed to conform to JEDEC
  114. * specifications
  115. */
  116. .txsr = 506, /* changed to conform to JEDEC
  117. * specifications
  118. */
  119. .cksrx = 5,
  120. .cksre = 5,
  121. .freq_chg_en = 0,
  122. .zqcl = 256,
  123. .zqinit = 512,
  124. .zqcs = 64,
  125. .ref_per_zq = 64,
  126. .zqcs_rotate = 0,
  127. .aprebit = 10,
  128. .cmd_age_cnt = 64,
  129. .age_cnt = 64,
  130. .q_fullness = 7,
  131. .odt_rd_mapcs0 = 0,
  132. .odt_wr_mapcs0 = 1,
  133. .wlmrd = 40,
  134. .wldqsen = 25,
  135. };
  136. ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
  137. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  138. return 0;
  139. }
  140. #ifdef CONFIG_VYBRID_GPIO
  141. static void setup_iomux_gpio(void)
  142. {
  143. static const iomux_v3_cfg_t gpio_pads[] = {
  144. VF610_PAD_PTA17__GPIO_7,
  145. VF610_PAD_PTA20__GPIO_10,
  146. VF610_PAD_PTA21__GPIO_11,
  147. VF610_PAD_PTA30__GPIO_20,
  148. VF610_PAD_PTA31__GPIO_21,
  149. VF610_PAD_PTB0__GPIO_22,
  150. VF610_PAD_PTB1__GPIO_23,
  151. VF610_PAD_PTB6__GPIO_28,
  152. VF610_PAD_PTB7__GPIO_29,
  153. VF610_PAD_PTB8__GPIO_30,
  154. VF610_PAD_PTB9__GPIO_31,
  155. VF610_PAD_PTB12__GPIO_34,
  156. VF610_PAD_PTB13__GPIO_35,
  157. VF610_PAD_PTB16__GPIO_38,
  158. VF610_PAD_PTB17__GPIO_39,
  159. VF610_PAD_PTB18__GPIO_40,
  160. VF610_PAD_PTB21__GPIO_43,
  161. VF610_PAD_PTB22__GPIO_44,
  162. VF610_PAD_PTC0__GPIO_45,
  163. VF610_PAD_PTC1__GPIO_46,
  164. VF610_PAD_PTC2__GPIO_47,
  165. VF610_PAD_PTC3__GPIO_48,
  166. VF610_PAD_PTC4__GPIO_49,
  167. VF610_PAD_PTC5__GPIO_50,
  168. VF610_PAD_PTC6__GPIO_51,
  169. VF610_PAD_PTC7__GPIO_52,
  170. VF610_PAD_PTC8__GPIO_53,
  171. VF610_PAD_PTD31__GPIO_63,
  172. VF610_PAD_PTD30__GPIO_64,
  173. VF610_PAD_PTD29__GPIO_65,
  174. VF610_PAD_PTD28__GPIO_66,
  175. VF610_PAD_PTD27__GPIO_67,
  176. VF610_PAD_PTD26__GPIO_68,
  177. VF610_PAD_PTD25__GPIO_69,
  178. VF610_PAD_PTD24__GPIO_70,
  179. VF610_PAD_PTD9__GPIO_88,
  180. VF610_PAD_PTD10__GPIO_89,
  181. VF610_PAD_PTD11__GPIO_90,
  182. VF610_PAD_PTD12__GPIO_91,
  183. VF610_PAD_PTD13__GPIO_92,
  184. VF610_PAD_PTB23__GPIO_93,
  185. VF610_PAD_PTB26__GPIO_96,
  186. VF610_PAD_PTB28__GPIO_98,
  187. VF610_PAD_PTC30__GPIO_103,
  188. VF610_PAD_PTA7__GPIO_134,
  189. };
  190. imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  191. }
  192. #endif
  193. #ifdef CONFIG_VIDEO_FSL_DCU_FB
  194. static void setup_iomux_fsl_dcu(void)
  195. {
  196. static const iomux_v3_cfg_t dcu0_pads[] = {
  197. VF610_PAD_PTE0__DCU0_HSYNC,
  198. VF610_PAD_PTE1__DCU0_VSYNC,
  199. VF610_PAD_PTE2__DCU0_PCLK,
  200. VF610_PAD_PTE4__DCU0_DE,
  201. VF610_PAD_PTE5__DCU0_R0,
  202. VF610_PAD_PTE6__DCU0_R1,
  203. VF610_PAD_PTE7__DCU0_R2,
  204. VF610_PAD_PTE8__DCU0_R3,
  205. VF610_PAD_PTE9__DCU0_R4,
  206. VF610_PAD_PTE10__DCU0_R5,
  207. VF610_PAD_PTE11__DCU0_R6,
  208. VF610_PAD_PTE12__DCU0_R7,
  209. VF610_PAD_PTE13__DCU0_G0,
  210. VF610_PAD_PTE14__DCU0_G1,
  211. VF610_PAD_PTE15__DCU0_G2,
  212. VF610_PAD_PTE16__DCU0_G3,
  213. VF610_PAD_PTE17__DCU0_G4,
  214. VF610_PAD_PTE18__DCU0_G5,
  215. VF610_PAD_PTE19__DCU0_G6,
  216. VF610_PAD_PTE20__DCU0_G7,
  217. VF610_PAD_PTE21__DCU0_B0,
  218. VF610_PAD_PTE22__DCU0_B1,
  219. VF610_PAD_PTE23__DCU0_B2,
  220. VF610_PAD_PTE24__DCU0_B3,
  221. VF610_PAD_PTE25__DCU0_B4,
  222. VF610_PAD_PTE26__DCU0_B5,
  223. VF610_PAD_PTE27__DCU0_B6,
  224. VF610_PAD_PTE28__DCU0_B7,
  225. };
  226. imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
  227. }
  228. static void setup_tcon(void)
  229. {
  230. setbits_le32(TCON0_BASE_ADDR, (1 << 29));
  231. }
  232. #endif
  233. static inline int is_colibri_vf61(void)
  234. {
  235. struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
  236. /*
  237. * Detect board type by Level 2 Cache: VF50 don't have any
  238. * Level 2 Cache.
  239. */
  240. return !!mscm->cpxcfg1;
  241. }
  242. static void clock_init(void)
  243. {
  244. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  245. struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
  246. u32 pfd_clk_sel, ddr_clk_sel;
  247. clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
  248. CCM_CCGR0_UART0_CTRL_MASK);
  249. #ifdef CONFIG_FSL_DSPI
  250. setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
  251. #endif
  252. clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
  253. CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
  254. clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
  255. CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
  256. CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
  257. CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
  258. clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
  259. CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
  260. clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
  261. CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
  262. CCM_CCGR4_GPC_CTRL_MASK);
  263. clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
  264. CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
  265. clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
  266. CCM_CCGR7_SDHC1_CTRL_MASK);
  267. clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
  268. CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
  269. clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
  270. CCM_CCGR10_NFC_CTRL_MASK);
  271. #ifdef CONFIG_USB_EHCI_VF
  272. setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
  273. setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
  274. clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
  275. ANADIG_PLL3_CTRL_POWERDOWN |
  276. ANADIG_PLL3_CTRL_DIV_SELECT,
  277. ANADIG_PLL3_CTRL_ENABLE);
  278. clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
  279. ANADIG_PLL7_CTRL_POWERDOWN |
  280. ANADIG_PLL7_CTRL_DIV_SELECT,
  281. ANADIG_PLL7_CTRL_ENABLE);
  282. #endif
  283. clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
  284. ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
  285. ANADIG_PLL5_CTRL_DIV_SELECT);
  286. if (is_colibri_vf61()) {
  287. clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
  288. ANADIG_PLL2_CTRL_POWERDOWN,
  289. ANADIG_PLL2_CTRL_ENABLE |
  290. ANADIG_PLL2_CTRL_DIV_SELECT);
  291. }
  292. clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
  293. ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
  294. clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
  295. CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
  296. /* See "Typical PLL Configuration" */
  297. if (is_colibri_vf61()) {
  298. pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
  299. ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
  300. } else {
  301. pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
  302. ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
  303. }
  304. clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
  305. CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
  306. CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
  307. CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
  308. CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
  309. ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
  310. CCM_CCSR_SYS_CLK_SEL(4));
  311. clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
  312. CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
  313. CCM_CACRR_ARM_CLK_DIV(0));
  314. clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
  315. CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
  316. CCM_CSCMR1_NFC_CLK_SEL(0));
  317. clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
  318. CCM_CSCDR1_RMII_CLK_EN);
  319. clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
  320. CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
  321. CCM_CSCDR2_NFC_EN);
  322. clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
  323. CCM_CSCDR3_NFC_PRE_DIV(3));
  324. clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
  325. CCM_CSCMR2_RMII_CLK_SEL(2));
  326. #ifdef CONFIG_VIDEO_FSL_DCU_FB
  327. setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
  328. setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
  329. #endif
  330. }
  331. static void mscm_init(void)
  332. {
  333. struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
  334. int i;
  335. for (i = 0; i < MSCM_IRSPRC_NUM; i++)
  336. writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
  337. }
  338. int board_early_init_f(void)
  339. {
  340. clock_init();
  341. mscm_init();
  342. #ifdef CONFIG_VYBRID_GPIO
  343. setup_iomux_gpio();
  344. #endif
  345. #ifdef CONFIG_VIDEO_FSL_DCU_FB
  346. setup_tcon();
  347. setup_iomux_fsl_dcu();
  348. #endif
  349. return 0;
  350. }
  351. #ifdef CONFIG_BOARD_LATE_INIT
  352. int board_late_init(void)
  353. {
  354. struct src *src = (struct src *)SRC_BASE_ADDR;
  355. if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
  356. == SRC_SBMR2_BMOD_SERIAL) {
  357. printf("Serial Downloader recovery mode, disable autoboot\n");
  358. env_set("bootdelay", "-1");
  359. }
  360. return 0;
  361. }
  362. #endif /* CONFIG_BOARD_LATE_INIT */
  363. int board_init(void)
  364. {
  365. struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
  366. /* address of boot parameters */
  367. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  368. /*
  369. * Enable external 32K Oscillator
  370. *
  371. * The internal clock experiences significant drift
  372. * so we must use the external oscillator in order
  373. * to maintain correct time in the hwclock
  374. */
  375. setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
  376. return 0;
  377. }
  378. int checkboard(void)
  379. {
  380. if (is_colibri_vf61())
  381. puts("Model: Toradex Colibri VF61\n");
  382. else
  383. puts("Model: Toradex Colibri VF50\n");
  384. return 0;
  385. }
  386. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  387. int ft_board_setup(void *blob, struct bd_info *bd)
  388. {
  389. #ifndef CONFIG_DM_VIDEO
  390. int ret = 0;
  391. #endif
  392. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  393. static const struct node_info nodes[] = {
  394. { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
  395. };
  396. /* Update partition nodes using info from mtdparts env var */
  397. puts(" Updating MTD partitions...\n");
  398. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  399. #endif
  400. #if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO)
  401. ret = fsl_dcu_fixedfb_setup(blob);
  402. if (ret)
  403. return ret;
  404. #endif
  405. return ft_common_board_setup(blob, bd);
  406. }
  407. #endif
  408. /*
  409. * Backlight off before OS handover
  410. */
  411. void board_preboot_os(void)
  412. {
  413. gpio_request(PTC0_GPIO_45, "BL_ON");
  414. gpio_direction_output(PTC0_GPIO_45, 0);
  415. }