evm.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * evm.c
  4. *
  5. * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
  6. * Antoine Tenart, <atenart@adeneo-embedded.com>
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <init.h>
  11. #include <net.h>
  12. #include <spl.h>
  13. #include <asm/cache.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/ddr_defs.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/arch/mmc_host_def.h>
  21. #include <asm/arch/mem.h>
  22. #include <asm/arch/mux.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int board_init(void)
  25. {
  26. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  27. #if defined(CONFIG_MTD_RAW_NAND)
  28. gpmc_init();
  29. #endif
  30. return 0;
  31. }
  32. int board_eth_init(struct bd_info *bis)
  33. {
  34. uint8_t mac_addr[6];
  35. uint32_t mac_hi, mac_lo;
  36. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  37. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  38. printf("<ethaddr> not set. Reading from E-fuse\n");
  39. /* try reading mac address from efuse */
  40. mac_lo = readl(&cdev->macid0l);
  41. mac_hi = readl(&cdev->macid0h);
  42. mac_addr[0] = mac_hi & 0xFF;
  43. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  44. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  45. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  46. mac_addr[4] = mac_lo & 0xFF;
  47. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  48. if (is_valid_ethaddr(mac_addr))
  49. eth_env_set_enetaddr("ethaddr", mac_addr);
  50. else
  51. printf("Unable to read MAC address. Set <ethaddr>\n");
  52. }
  53. return 0;
  54. }
  55. #ifdef CONFIG_SPL_BUILD
  56. static struct module_pin_mux mmc_pin_mux[] = {
  57. { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
  58. { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
  59. { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  60. { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  61. { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  62. { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  63. { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  64. { -1 },
  65. };
  66. void set_uart_mux_conf(void) {}
  67. void set_mux_conf_regs(void)
  68. {
  69. configure_module_pin_mux(mmc_pin_mux);
  70. }
  71. /*
  72. * EMIF Paramters. Refer the EMIF register documentation and the
  73. * memory datasheet for details. This is for 796 MHz.
  74. */
  75. #define EMIF_TIM1 0x1779C9FE
  76. #define EMIF_TIM2 0x50608074
  77. #define EMIF_TIM3 0x009F857F
  78. #define EMIF_SDREF 0x10001841
  79. #define EMIF_SDCFG 0x62A73832
  80. #define EMIF_PHYCFG 0x00000110
  81. static const struct emif_regs ddr3_emif_regs = {
  82. .sdram_config = EMIF_SDCFG,
  83. .ref_ctrl = EMIF_SDREF,
  84. .sdram_tim1 = EMIF_TIM1,
  85. .sdram_tim2 = EMIF_TIM2,
  86. .sdram_tim3 = EMIF_TIM3,
  87. .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
  88. };
  89. static const struct cmd_control ddr3_ctrl = {
  90. .cmd0csratio = 0x100,
  91. .cmd0iclkout = 0x001,
  92. .cmd1csratio = 0x100,
  93. .cmd1iclkout = 0x001,
  94. .cmd2csratio = 0x100,
  95. .cmd2iclkout = 0x001,
  96. };
  97. /* These values are obtained from the CCS app */
  98. #define RD_DQS_GATE (0x1B3)
  99. #define RD_DQS (0x35)
  100. #define WR_DQS (0x93)
  101. static struct ddr_data ddr3_data = {
  102. .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
  103. .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
  104. .datawiratio0 = ((0x20<<10) | 0x20<<0),
  105. .datagiratio0 = ((0x20<<10) | 0x20<<0),
  106. .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
  107. .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
  108. };
  109. static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
  110. .dmm_lisa_map_0 = 0x00000000,
  111. .dmm_lisa_map_1 = 0x00000000,
  112. .dmm_lisa_map_2 = 0x80640300,
  113. .dmm_lisa_map_3 = 0xC0640320,
  114. };
  115. void sdram_init(void)
  116. {
  117. /*
  118. * Pass in our DDR3 config information and that we have 2 EMIFs to
  119. * configure.
  120. */
  121. config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
  122. &evm_lisa_map_regs, 2);
  123. }
  124. #endif /* CONFIG_SPL_BUILD */