board.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM43XX based boards
  6. *
  7. * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <eeprom.h>
  11. #include <image.h>
  12. #include <dm/uclass.h>
  13. #include <env.h>
  14. #include <fdt_support.h>
  15. #include <i2c.h>
  16. #include <init.h>
  17. #include <net.h>
  18. #include <linux/errno.h>
  19. #include <spl.h>
  20. #include <usb.h>
  21. #include <asm/omap_sec_common.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/arch/mux.h>
  25. #include <asm/arch/ddr_defs.h>
  26. #include <asm/arch/gpio.h>
  27. #include <asm/emif.h>
  28. #include <asm/omap_common.h>
  29. #include "../common/board_detect.h"
  30. #include "board.h"
  31. #include <power/pmic.h>
  32. #include <power/tps65218.h>
  33. #include <power/tps62362.h>
  34. #include <linux/usb/gadget.h>
  35. #include <dwc3-uboot.h>
  36. #include <dwc3-omap-uboot.h>
  37. #include <ti-usb-phy-uboot.h>
  38. DECLARE_GLOBAL_DATA_PTR;
  39. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  40. /*
  41. * Read header information from EEPROM into global structure.
  42. */
  43. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  44. void do_board_detect(void)
  45. {
  46. /* Ensure I2C is initialized for EEPROM access*/
  47. gpi2c_init();
  48. if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  49. CONFIG_EEPROM_CHIP_ADDRESS))
  50. printf("ti_i2c_eeprom_init failed\n");
  51. }
  52. #endif
  53. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  54. const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  55. { /* 19.2 MHz */
  56. {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
  57. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  58. {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
  59. {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
  60. {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
  61. {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
  62. },
  63. { /* 24 MHz */
  64. {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
  65. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  66. {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
  67. {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
  68. {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
  69. {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
  70. },
  71. { /* 25 MHz */
  72. {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
  73. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  74. {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
  75. {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
  76. {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
  77. {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
  78. },
  79. { /* 26 MHz */
  80. {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
  81. {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
  82. {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
  83. {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
  84. {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
  85. {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
  86. },
  87. };
  88. const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  89. {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
  90. {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
  91. {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
  92. {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
  93. };
  94. const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
  95. {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  96. {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
  97. {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
  98. {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
  99. };
  100. const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
  101. {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
  102. {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
  103. {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
  104. {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
  105. };
  106. const struct dpll_params gp_evm_dpll_ddr = {
  107. 50, 2, 1, -1, 2, -1, -1};
  108. static const struct dpll_params idk_dpll_ddr = {
  109. 400, 23, 1, -1, 2, -1, -1
  110. };
  111. static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
  112. 0x00500050,
  113. 0x00350035,
  114. 0x00350035,
  115. 0x00350035,
  116. 0x00350035,
  117. 0x00350035,
  118. 0x00000000,
  119. 0x00000000,
  120. 0x00000000,
  121. 0x00000000,
  122. 0x00000000,
  123. 0x00000000,
  124. 0x00000000,
  125. 0x00000000,
  126. 0x00000000,
  127. 0x00000000,
  128. 0x00000000,
  129. 0x00000000,
  130. 0x40001000,
  131. 0x08102040
  132. };
  133. const struct ctrl_ioregs ioregs_lpddr2 = {
  134. .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
  135. .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
  136. .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
  137. .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
  138. .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
  139. .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
  140. .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
  141. .emif_sdram_config_ext = 0x1,
  142. };
  143. const struct emif_regs emif_regs_lpddr2 = {
  144. .sdram_config = 0x808012BA,
  145. .ref_ctrl = 0x0000040D,
  146. .sdram_tim1 = 0xEA86B411,
  147. .sdram_tim2 = 0x103A094A,
  148. .sdram_tim3 = 0x0F6BA37F,
  149. .read_idle_ctrl = 0x00050000,
  150. .zq_config = 0x50074BE4,
  151. .temp_alert_config = 0x0,
  152. .emif_rd_wr_lvl_rmp_win = 0x0,
  153. .emif_rd_wr_lvl_rmp_ctl = 0x0,
  154. .emif_rd_wr_lvl_ctl = 0x0,
  155. .emif_ddr_phy_ctlr_1 = 0x0E284006,
  156. .emif_rd_wr_exec_thresh = 0x80000405,
  157. .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
  158. .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
  159. .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
  160. .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
  161. .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
  162. .emif_prio_class_serv_map = 0x80000001,
  163. .emif_connect_id_serv_1_map = 0x80000094,
  164. .emif_connect_id_serv_2_map = 0x00000000,
  165. .emif_cos_config = 0x000FFFFF
  166. };
  167. const struct ctrl_ioregs ioregs_ddr3 = {
  168. .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
  169. .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
  170. .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
  171. .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
  172. .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
  173. .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  174. .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  175. .emif_sdram_config_ext = 0xc163,
  176. };
  177. const struct emif_regs ddr3_emif_regs_400Mhz = {
  178. .sdram_config = 0x638413B2,
  179. .ref_ctrl = 0x00000C30,
  180. .sdram_tim1 = 0xEAAAD4DB,
  181. .sdram_tim2 = 0x266B7FDA,
  182. .sdram_tim3 = 0x107F8678,
  183. .read_idle_ctrl = 0x00050000,
  184. .zq_config = 0x50074BE4,
  185. .temp_alert_config = 0x0,
  186. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  187. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  188. .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
  189. .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
  190. .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
  191. .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
  192. .emif_rd_wr_lvl_rmp_win = 0x0,
  193. .emif_rd_wr_lvl_rmp_ctl = 0x0,
  194. .emif_rd_wr_lvl_ctl = 0x0,
  195. .emif_rd_wr_exec_thresh = 0x80000405,
  196. .emif_prio_class_serv_map = 0x80000001,
  197. .emif_connect_id_serv_1_map = 0x80000094,
  198. .emif_connect_id_serv_2_map = 0x00000000,
  199. .emif_cos_config = 0x000FFFFF
  200. };
  201. /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
  202. const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
  203. .sdram_config = 0x638413B2,
  204. .ref_ctrl = 0x00000C30,
  205. .sdram_tim1 = 0xEAAAD4DB,
  206. .sdram_tim2 = 0x266B7FDA,
  207. .sdram_tim3 = 0x107F8678,
  208. .read_idle_ctrl = 0x00050000,
  209. .zq_config = 0x50074BE4,
  210. .temp_alert_config = 0x0,
  211. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  212. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  213. .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
  214. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  215. .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
  216. .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
  217. .emif_rd_wr_exec_thresh = 0x80000405,
  218. .emif_prio_class_serv_map = 0x80000001,
  219. .emif_connect_id_serv_1_map = 0x80000094,
  220. .emif_connect_id_serv_2_map = 0x00000000,
  221. .emif_cos_config = 0x000FFFFF
  222. };
  223. /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
  224. const struct emif_regs ddr3_emif_regs_400Mhz_production = {
  225. .sdram_config = 0x638413B2,
  226. .ref_ctrl = 0x00000C30,
  227. .sdram_tim1 = 0xEAAAD4DB,
  228. .sdram_tim2 = 0x266B7FDA,
  229. .sdram_tim3 = 0x107F8678,
  230. .read_idle_ctrl = 0x00050000,
  231. .zq_config = 0x50074BE4,
  232. .temp_alert_config = 0x0,
  233. .emif_ddr_phy_ctlr_1 = 0x00048008,
  234. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  235. .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
  236. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  237. .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
  238. .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
  239. .emif_rd_wr_exec_thresh = 0x80000405,
  240. .emif_prio_class_serv_map = 0x80000001,
  241. .emif_connect_id_serv_1_map = 0x80000094,
  242. .emif_connect_id_serv_2_map = 0x00000000,
  243. .emif_cos_config = 0x000FFFFF
  244. };
  245. static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
  246. .sdram_config = 0x638413b2,
  247. .sdram_config2 = 0x00000000,
  248. .ref_ctrl = 0x00000c30,
  249. .sdram_tim1 = 0xeaaad4db,
  250. .sdram_tim2 = 0x266b7fda,
  251. .sdram_tim3 = 0x107f8678,
  252. .read_idle_ctrl = 0x00050000,
  253. .zq_config = 0x50074be4,
  254. .temp_alert_config = 0x0,
  255. .emif_ddr_phy_ctlr_1 = 0x0e084008,
  256. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  257. .emif_ddr_ext_phy_ctrl_2 = 0x89,
  258. .emif_ddr_ext_phy_ctrl_3 = 0x90,
  259. .emif_ddr_ext_phy_ctrl_4 = 0x8e,
  260. .emif_ddr_ext_phy_ctrl_5 = 0x8d,
  261. .emif_rd_wr_lvl_rmp_win = 0x0,
  262. .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  263. .emif_rd_wr_lvl_ctl = 0x00000000,
  264. .emif_rd_wr_exec_thresh = 0x80000000,
  265. .emif_prio_class_serv_map = 0x80000001,
  266. .emif_connect_id_serv_1_map = 0x80000094,
  267. .emif_connect_id_serv_2_map = 0x00000000,
  268. .emif_cos_config = 0x000FFFFF
  269. };
  270. static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
  271. .sdram_config = 0x61a11b32,
  272. .sdram_config2 = 0x00000000,
  273. .ref_ctrl = 0x00000c30,
  274. .sdram_tim1 = 0xeaaad4db,
  275. .sdram_tim2 = 0x266b7fda,
  276. .sdram_tim3 = 0x107f8678,
  277. .read_idle_ctrl = 0x00050000,
  278. .zq_config = 0x50074be4,
  279. .temp_alert_config = 0x00000000,
  280. .emif_ddr_phy_ctlr_1 = 0x00008009,
  281. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  282. .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
  283. .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
  284. .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
  285. .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
  286. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  287. .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
  288. .emif_rd_wr_lvl_ctl = 0x00000000,
  289. .emif_rd_wr_exec_thresh = 0x00000405,
  290. .emif_prio_class_serv_map = 0x00000000,
  291. .emif_connect_id_serv_1_map = 0x00000000,
  292. .emif_connect_id_serv_2_map = 0x00000000,
  293. .emif_cos_config = 0x00ffffff
  294. };
  295. void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
  296. {
  297. if (board_is_eposevm()) {
  298. *regs = ext_phy_ctrl_const_base_lpddr2;
  299. *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
  300. }
  301. return;
  302. }
  303. const struct dpll_params *get_dpll_ddr_params(void)
  304. {
  305. int ind = get_sys_clk_index();
  306. if (board_is_eposevm())
  307. return &epos_evm_dpll_ddr[ind];
  308. else if (board_is_evm() || board_is_sk())
  309. return &gp_evm_dpll_ddr;
  310. else if (board_is_idk())
  311. return &idk_dpll_ddr;
  312. printf(" Board '%s' not supported\n", board_ti_get_name());
  313. return NULL;
  314. }
  315. /*
  316. * get_opp_offset:
  317. * Returns the index for safest OPP of the device to boot.
  318. * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
  319. * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
  320. * This data is read from dev_attribute register which is e-fused.
  321. * A'1' in bit indicates OPP disabled and not available, a '0' indicates
  322. * OPP available. Lowest OPP starts with min_off. So returning the
  323. * bit with rightmost '0'.
  324. */
  325. static int get_opp_offset(int max_off, int min_off)
  326. {
  327. struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
  328. int opp, offset, i;
  329. /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
  330. opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
  331. for (i = max_off; i >= min_off; i--) {
  332. offset = opp & (1 << i);
  333. if (!offset)
  334. return i;
  335. }
  336. return min_off;
  337. }
  338. const struct dpll_params *get_dpll_mpu_params(void)
  339. {
  340. int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
  341. u32 ind = get_sys_clk_index();
  342. return &dpll_mpu[ind][opp];
  343. }
  344. const struct dpll_params *get_dpll_core_params(void)
  345. {
  346. int ind = get_sys_clk_index();
  347. return &dpll_core[ind];
  348. }
  349. const struct dpll_params *get_dpll_per_params(void)
  350. {
  351. int ind = get_sys_clk_index();
  352. return &dpll_per[ind];
  353. }
  354. void scale_vcores_generic(u32 m)
  355. {
  356. int mpu_vdd, ddr_volt;
  357. #ifndef CONFIG_DM_I2C
  358. if (i2c_probe(TPS65218_CHIP_PM))
  359. return;
  360. #else
  361. if (power_tps65218_init(0))
  362. return;
  363. #endif
  364. switch (m) {
  365. case 1000:
  366. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
  367. break;
  368. case 800:
  369. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
  370. break;
  371. case 720:
  372. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
  373. break;
  374. case 600:
  375. mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
  376. break;
  377. case 300:
  378. mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
  379. break;
  380. default:
  381. puts("Unknown MPU clock, not scaling\n");
  382. return;
  383. }
  384. /* Set DCDC1 (CORE) voltage to 1.1V */
  385. if (tps65218_voltage_update(TPS65218_DCDC1,
  386. TPS65218_DCDC_VOLT_SEL_1100MV)) {
  387. printf("%s failure\n", __func__);
  388. return;
  389. }
  390. /* Set DCDC2 (MPU) voltage */
  391. if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
  392. printf("%s failure\n", __func__);
  393. return;
  394. }
  395. if (board_is_eposevm())
  396. ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
  397. else
  398. ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
  399. /* Set DCDC3 (DDR) voltage */
  400. if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
  401. printf("%s failure\n", __func__);
  402. return;
  403. }
  404. }
  405. void scale_vcores_idk(u32 m)
  406. {
  407. int mpu_vdd;
  408. #ifndef CONFIG_DM_I2C
  409. if (i2c_probe(TPS62362_I2C_ADDR))
  410. return;
  411. #else
  412. if (power_tps62362_init(0))
  413. return;
  414. #endif
  415. switch (m) {
  416. case 1000:
  417. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
  418. break;
  419. case 800:
  420. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
  421. break;
  422. case 720:
  423. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
  424. break;
  425. case 600:
  426. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
  427. break;
  428. case 300:
  429. mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
  430. break;
  431. default:
  432. puts("Unknown MPU clock, not scaling\n");
  433. return;
  434. }
  435. /* Set VDD_MPU voltage */
  436. if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
  437. printf("%s failure\n", __func__);
  438. return;
  439. }
  440. }
  441. void gpi2c_init(void)
  442. {
  443. /* When needed to be invoked prior to BSS initialization */
  444. static bool first_time = true;
  445. if (first_time) {
  446. enable_i2c0_pin_mux();
  447. #ifndef CONFIG_DM_I2C
  448. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  449. CONFIG_SYS_OMAP24_I2C_SLAVE);
  450. #endif
  451. first_time = false;
  452. }
  453. }
  454. void scale_vcores(void)
  455. {
  456. const struct dpll_params *mpu_params;
  457. /* Ensure I2C is initialized for PMIC configuration */
  458. gpi2c_init();
  459. /* Get the frequency */
  460. mpu_params = get_dpll_mpu_params();
  461. if (board_is_idk())
  462. scale_vcores_idk(mpu_params->m);
  463. else
  464. scale_vcores_generic(mpu_params->m);
  465. }
  466. void set_uart_mux_conf(void)
  467. {
  468. enable_uart0_pin_mux();
  469. }
  470. void set_mux_conf_regs(void)
  471. {
  472. enable_board_pin_mux();
  473. }
  474. static void enable_vtt_regulator(void)
  475. {
  476. u32 temp;
  477. /* enable module */
  478. writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
  479. /* enable output for GPIO5_7 */
  480. writel(GPIO_SETDATAOUT(7),
  481. AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
  482. temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
  483. temp = temp & ~(GPIO_OE_ENABLE(7));
  484. writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
  485. }
  486. enum {
  487. RTC_BOARD_EPOS = 1,
  488. RTC_BOARD_EVM14,
  489. RTC_BOARD_EVM12,
  490. RTC_BOARD_GPEVM,
  491. RTC_BOARD_SK,
  492. };
  493. /*
  494. * In the rtc_only+DRR in self-refresh boot path we have the board type info
  495. * in the rtc scratch pad register hence we bypass the costly i2c reads to
  496. * eeprom and directly programthe board name string
  497. */
  498. void rtc_only_update_board_type(u32 btype)
  499. {
  500. const char *name = "";
  501. const char *rev = "1.0";
  502. switch (btype) {
  503. case RTC_BOARD_EPOS:
  504. name = "AM43EPOS";
  505. break;
  506. case RTC_BOARD_EVM14:
  507. name = "AM43__GP";
  508. rev = "1.4";
  509. break;
  510. case RTC_BOARD_EVM12:
  511. name = "AM43__GP";
  512. rev = "1.2";
  513. break;
  514. case RTC_BOARD_GPEVM:
  515. name = "AM43__GP";
  516. break;
  517. case RTC_BOARD_SK:
  518. name = "AM43__SK";
  519. break;
  520. }
  521. ti_i2c_eeprom_am_set(name, rev);
  522. }
  523. u32 rtc_only_get_board_type(void)
  524. {
  525. if (board_is_eposevm())
  526. return RTC_BOARD_EPOS;
  527. else if (board_is_evm_14_or_later())
  528. return RTC_BOARD_EVM14;
  529. else if (board_is_evm_12_or_later())
  530. return RTC_BOARD_EVM12;
  531. else if (board_is_gpevm())
  532. return RTC_BOARD_GPEVM;
  533. else if (board_is_sk())
  534. return RTC_BOARD_SK;
  535. return 0;
  536. }
  537. void sdram_init(void)
  538. {
  539. /*
  540. * EPOS EVM has 1GB LPDDR2 connected to EMIF.
  541. * GP EMV has 1GB DDR3 connected to EMIF
  542. * along with VTT regulator.
  543. */
  544. if (board_is_eposevm()) {
  545. config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
  546. } else if (board_is_evm_14_or_later()) {
  547. enable_vtt_regulator();
  548. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  549. &ddr3_emif_regs_400Mhz_production, 0);
  550. } else if (board_is_evm_12_or_later()) {
  551. enable_vtt_regulator();
  552. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  553. &ddr3_emif_regs_400Mhz_beta, 0);
  554. } else if (board_is_evm()) {
  555. enable_vtt_regulator();
  556. config_ddr(0, &ioregs_ddr3, NULL, NULL,
  557. &ddr3_emif_regs_400Mhz, 0);
  558. } else if (board_is_sk()) {
  559. config_ddr(400, &ioregs_ddr3, NULL, NULL,
  560. &ddr3_sk_emif_regs_400Mhz, 0);
  561. } else if (board_is_idk()) {
  562. config_ddr(400, &ioregs_ddr3, NULL, NULL,
  563. &ddr3_idk_emif_regs_400Mhz, 0);
  564. }
  565. }
  566. #endif
  567. /* setup board specific PMIC */
  568. int power_init_board(void)
  569. {
  570. int rc;
  571. #ifndef CONFIG_DM_I2C
  572. struct pmic *p = NULL;
  573. #endif
  574. if (board_is_idk()) {
  575. rc = power_tps62362_init(0);
  576. if (rc)
  577. goto done;
  578. #ifndef CONFIG_DM_I2C
  579. p = pmic_get("TPS62362");
  580. if (!p || pmic_probe(p))
  581. goto done;
  582. #endif
  583. puts("PMIC: TPS62362\n");
  584. } else {
  585. rc = power_tps65218_init(0);
  586. if (rc)
  587. goto done;
  588. #ifndef CONFIG_DM_I2C
  589. p = pmic_get("TPS65218_PMIC");
  590. if (!p || pmic_probe(p))
  591. goto done;
  592. #endif
  593. puts("PMIC: TPS65218\n");
  594. }
  595. done:
  596. return 0;
  597. }
  598. int board_init(void)
  599. {
  600. struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
  601. u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
  602. modena_init0_bw_integer, modena_init0_watermark_0;
  603. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  604. gpmc_init();
  605. /*
  606. * Call this to initialize *ctrl again
  607. */
  608. hw_data_init();
  609. /* Clear all important bits for DSS errata that may need to be tweaked*/
  610. mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
  611. MREQPRIO_0_SAB_INIT0_MASK;
  612. mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
  613. modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
  614. BW_LIMITER_BW_FRAC_MASK;
  615. modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
  616. BW_LIMITER_BW_INT_MASK;
  617. modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
  618. BW_LIMITER_BW_WATERMARK_MASK;
  619. /* Setting MReq Priority of the DSS*/
  620. mreqprio_0 |= 0x77;
  621. /*
  622. * Set L3 Fast Configuration Register
  623. * Limiting bandwith for ARM core to 700 MBPS
  624. */
  625. modena_init0_bw_fractional |= 0x10;
  626. modena_init0_bw_integer |= 0x3;
  627. writel(mreqprio_0, &cdev->mreqprio_0);
  628. writel(mreqprio_1, &cdev->mreqprio_1);
  629. writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
  630. writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
  631. writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
  632. return 0;
  633. }
  634. #ifdef CONFIG_BOARD_LATE_INIT
  635. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  636. static int device_okay(const char *path)
  637. {
  638. int node;
  639. node = fdt_path_offset(gd->fdt_blob, path);
  640. if (node < 0)
  641. return 0;
  642. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  643. }
  644. #endif
  645. int board_late_init(void)
  646. {
  647. struct udevice *dev;
  648. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  649. set_board_info_env(NULL);
  650. /*
  651. * Default FIT boot on HS devices. Non FIT images are not allowed
  652. * on HS devices.
  653. */
  654. if (get_device_type() == HS_DEVICE)
  655. env_set("boot_fit", "1");
  656. #endif
  657. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  658. if (device_okay("/ocp/omap_dwc3@48380000"))
  659. enable_usb_clocks(0);
  660. if (device_okay("/ocp/omap_dwc3@483c0000"))
  661. enable_usb_clocks(1);
  662. #endif
  663. /* Just probe the potentially supported cdce913 device */
  664. uclass_get_device(UCLASS_CLK, 0, &dev);
  665. return 0;
  666. }
  667. #endif
  668. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  669. #ifdef CONFIG_USB_DWC3
  670. static struct dwc3_device usb_otg_ss1 = {
  671. .maximum_speed = USB_SPEED_HIGH,
  672. .base = USB_OTG_SS1_BASE,
  673. .tx_fifo_resize = false,
  674. .index = 0,
  675. };
  676. static struct dwc3_omap_device usb_otg_ss1_glue = {
  677. .base = (void *)USB_OTG_SS1_GLUE_BASE,
  678. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  679. .index = 0,
  680. };
  681. static struct ti_usb_phy_device usb_phy1_device = {
  682. .usb2_phy_power = (void *)USB2_PHY1_POWER,
  683. .index = 0,
  684. };
  685. static struct dwc3_device usb_otg_ss2 = {
  686. .maximum_speed = USB_SPEED_HIGH,
  687. .base = USB_OTG_SS2_BASE,
  688. .tx_fifo_resize = false,
  689. .index = 1,
  690. };
  691. static struct dwc3_omap_device usb_otg_ss2_glue = {
  692. .base = (void *)USB_OTG_SS2_GLUE_BASE,
  693. .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
  694. .index = 1,
  695. };
  696. static struct ti_usb_phy_device usb_phy2_device = {
  697. .usb2_phy_power = (void *)USB2_PHY2_POWER,
  698. .index = 1,
  699. };
  700. int usb_gadget_handle_interrupts(int index)
  701. {
  702. u32 status;
  703. status = dwc3_omap_uboot_interrupt_status(index);
  704. if (status)
  705. dwc3_uboot_handle_interrupt(index);
  706. return 0;
  707. }
  708. #endif /* CONFIG_USB_DWC3 */
  709. #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
  710. int board_usb_init(int index, enum usb_init_type init)
  711. {
  712. enable_usb_clocks(index);
  713. #ifdef CONFIG_USB_DWC3
  714. switch (index) {
  715. case 0:
  716. if (init == USB_INIT_DEVICE) {
  717. usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
  718. usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  719. dwc3_omap_uboot_init(&usb_otg_ss1_glue);
  720. ti_usb_phy_uboot_init(&usb_phy1_device);
  721. dwc3_uboot_init(&usb_otg_ss1);
  722. }
  723. break;
  724. case 1:
  725. if (init == USB_INIT_DEVICE) {
  726. usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
  727. usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
  728. ti_usb_phy_uboot_init(&usb_phy2_device);
  729. dwc3_omap_uboot_init(&usb_otg_ss2_glue);
  730. dwc3_uboot_init(&usb_otg_ss2);
  731. }
  732. break;
  733. default:
  734. printf("Invalid Controller Index\n");
  735. }
  736. #endif
  737. return 0;
  738. }
  739. int board_usb_cleanup(int index, enum usb_init_type init)
  740. {
  741. #ifdef CONFIG_USB_DWC3
  742. switch (index) {
  743. case 0:
  744. case 1:
  745. if (init == USB_INIT_DEVICE) {
  746. ti_usb_phy_uboot_exit(index);
  747. dwc3_uboot_exit(index);
  748. dwc3_omap_uboot_exit(index);
  749. }
  750. break;
  751. default:
  752. printf("Invalid Controller Index\n");
  753. }
  754. #endif
  755. disable_usb_clocks(index);
  756. return 0;
  757. }
  758. #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
  759. #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  760. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  761. int ft_board_setup(void *blob, struct bd_info *bd)
  762. {
  763. ft_cpu_setup(blob, bd);
  764. return 0;
  765. }
  766. #endif
  767. #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
  768. int board_fit_config_name_match(const char *name)
  769. {
  770. bool eeprom_read = board_ti_was_eeprom_read();
  771. if (!strcmp(name, "am4372-generic") && !eeprom_read)
  772. return 0;
  773. else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
  774. return 0;
  775. else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
  776. return 0;
  777. else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
  778. return 0;
  779. else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
  780. return 0;
  781. else
  782. return -1;
  783. }
  784. #endif
  785. #ifdef CONFIG_DTB_RESELECT
  786. int embedded_dtb_select(void)
  787. {
  788. do_board_detect();
  789. fdtdec_setup();
  790. return 0;
  791. }
  792. #endif
  793. #ifdef CONFIG_TI_SECURE_DEVICE
  794. void board_fit_image_post_process(void **p_image, size_t *p_size)
  795. {
  796. secure_boot_verify_image(p_image, p_size);
  797. }
  798. void board_tee_image_process(ulong tee_image, size_t tee_size)
  799. {
  800. secure_tee_install((u32)tee_image);
  801. }
  802. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  803. #endif