theadorable.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2019 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <console.h>
  8. #include <i2c.h>
  9. #include <init.h>
  10. #include <net.h>
  11. #include <pci.h>
  12. #if !defined(CONFIG_SPL_BUILD)
  13. #include <bootcount.h>
  14. #endif
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/soc.h>
  19. #include <linux/delay.h>
  20. #include <linux/mbus.h>
  21. #ifdef CONFIG_NET
  22. #include <netdev.h>
  23. #endif
  24. #include <u-boot/crc.h>
  25. #include "theadorable.h"
  26. #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
  27. #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
  30. #define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
  31. (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
  32. #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
  33. #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
  34. #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
  35. #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
  36. #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
  37. #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
  38. #define GPIO_USB0_PWR_ON 18
  39. #define GPIO_USB1_PWR_ON 19
  40. #define PEX_SWITCH_NOT_FOUNT_LIMIT 3
  41. #define STM_I2C_BUS 1
  42. #define STM_I2C_ADDR 0x27
  43. #define REBOOT_DELAY 1000 /* reboot-delay in ms */
  44. #define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */
  45. /* DDR3 static configuration */
  46. static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
  47. {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
  48. {0x00001404, 0x30000800}, /* Dunit Control Low Register */
  49. {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
  50. {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
  51. {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
  52. {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
  53. {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
  54. {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
  55. {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
  56. {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
  57. {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
  58. {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
  59. {0x000014A8, 0x00000101}, /* AXI Control Register */
  60. /*
  61. * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
  62. * training sequence
  63. */
  64. {0x000200e8, 0x3fff0e01},
  65. {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
  66. {0x0001504, 0x7fffffe1}, /* CS0 Size */
  67. {0x000150C, 0x00000000}, /* CS1 Size */
  68. {0x0001514, 0x00000000}, /* CS2 Size */
  69. {0x000151C, 0x00000000}, /* CS3 Size */
  70. {0x00020220, 0x00000007}, /* Reserved */
  71. {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
  72. {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
  73. {0x000015D0, 0x00000650}, /* MR0 */
  74. {0x000015D4, 0x00000044}, /* MR1 */
  75. {0x000015D8, 0x00000010}, /* MR2 */
  76. {0x000015DC, 0x00000000}, /* MR3 */
  77. {0x000015E0, 0x00000001},
  78. {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
  79. {0x000015EC, 0xf800a225}, /* DDR PHY */
  80. /* Recommended Settings from Marvell for 4 x 16 bit devices: */
  81. {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
  82. {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
  83. {0x0, 0x0}
  84. };
  85. static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
  86. {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
  87. };
  88. extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
  89. /*
  90. * Lane0 - PCIE0.0 X1 (to WIFI Module)
  91. * Lane5 - SATA0
  92. * Lane6 - SATA1
  93. * Lane7 - SGMII0 (to Ethernet Phy)
  94. * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
  95. * all other lanes are disabled
  96. */
  97. MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
  98. { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
  99. { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
  100. PEX_BUS_DISABLED },
  101. 0x0060, serdes_change_m_phy
  102. },
  103. };
  104. /*
  105. * Define a board-specific detection pulse-width array for the SerDes PCIe
  106. * interfaces. If not defined in the board code, the default of currently 2
  107. * is used. Values from 0...3 are possible (2 bits).
  108. */
  109. u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
  110. MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
  111. {
  112. /* Only one mode supported for this board */
  113. return &board_ddr_modes[0];
  114. }
  115. MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
  116. {
  117. return &theadorable_serdes_cfg[0];
  118. }
  119. u8 board_sat_r_get(u8 dev_num, u8 reg)
  120. {
  121. /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
  122. return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
  123. }
  124. int board_early_init_f(void)
  125. {
  126. /* Configure MPP */
  127. writel(0x00000000, MVEBU_MPP_BASE + 0x00);
  128. writel(0x03300000, MVEBU_MPP_BASE + 0x04);
  129. writel(0x00000033, MVEBU_MPP_BASE + 0x08);
  130. writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
  131. writel(0x11110000, MVEBU_MPP_BASE + 0x10);
  132. writel(0x00221100, MVEBU_MPP_BASE + 0x14);
  133. writel(0x00000000, MVEBU_MPP_BASE + 0x18);
  134. writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
  135. writel(0x00000000, MVEBU_MPP_BASE + 0x20);
  136. /* Configure GPIO */
  137. writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  138. writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  139. writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  140. writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  141. writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
  142. writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
  143. return 0;
  144. }
  145. int board_init(void)
  146. {
  147. int ret;
  148. /* adress of boot parameters */
  149. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  150. /*
  151. * Map SPI devices via MBUS so that they can be accessed via
  152. * the SPI direct access mode
  153. */
  154. mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
  155. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
  156. mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
  157. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
  158. /*
  159. * Set RX Channel Control 0 Register:
  160. * Tests have shown, that setting the LPF_COEF from 0 (1/8)
  161. * to 3 (1/1) results in a more stable USB connection.
  162. */
  163. setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
  164. setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
  165. setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
  166. /* Toggle USB power */
  167. ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
  168. if (ret < 0)
  169. return ret;
  170. gpio_direction_output(GPIO_USB0_PWR_ON, 0);
  171. ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
  172. if (ret < 0)
  173. return ret;
  174. gpio_direction_output(GPIO_USB1_PWR_ON, 0);
  175. mdelay(1);
  176. gpio_set_value(GPIO_USB0_PWR_ON, 1);
  177. gpio_set_value(GPIO_USB1_PWR_ON, 1);
  178. return 0;
  179. }
  180. int checkboard(void)
  181. {
  182. board_fpga_add();
  183. return 0;
  184. }
  185. #ifdef CONFIG_NET
  186. int board_eth_init(struct bd_info *bis)
  187. {
  188. cpu_eth_init(bis); /* Built in controller(s) come first */
  189. return pci_eth_init(bis);
  190. }
  191. #endif
  192. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
  193. int board_late_init(void)
  194. {
  195. pci_dev_t bdf;
  196. ulong bootcount;
  197. /*
  198. * Check if the PEX switch is detected (somtimes its not available
  199. * on the PCIe bus). In this case, try to recover by issuing a
  200. * soft-reset or even a power-cycle, depending on the bootcounter
  201. * value.
  202. */
  203. bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
  204. if (bdf == -1) {
  205. unsigned long start_time = get_timer(0);
  206. u8 i2c_buf[8];
  207. int ret;
  208. /* PEX switch not found! */
  209. bootcount = bootcount_load();
  210. printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
  211. bootcount);
  212. /*
  213. * The user can exit this boot-loop in the error case by
  214. * hitting Ctrl-C. So wait some time for this key here.
  215. */
  216. printf("Continue booting with Ctrl-C, otherwise rebooting\n");
  217. do {
  218. /* Handle control-c and timeouts */
  219. if (ctrlc()) {
  220. printf("PEX error boot-loop aborted!\n");
  221. return 0;
  222. }
  223. } while (get_timer(start_time) < ABORT_TIMEOUT);
  224. /*
  225. * At this stage the bootcounter has not been incremented
  226. * yet. We need to do this manually here to get an actually
  227. * working bootcounter in this error case.
  228. */
  229. bootcount_inc();
  230. if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
  231. printf("Issuing power-switch via uC!\n");
  232. printf("Issuing power-switch via uC!\n");
  233. i2c_set_bus_num(STM_I2C_BUS);
  234. i2c_buf[0] = STM_I2C_ADDR << 1;
  235. i2c_buf[1] = 0xc5; /* cmd */
  236. i2c_buf[2] = 0x01; /* enable */
  237. /* Delay before reboot */
  238. i2c_buf[3] = REBOOT_DELAY & 0x00ff;
  239. i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
  240. /* Delay before shutdown */
  241. i2c_buf[5] = 0x00;
  242. i2c_buf[6] = 0x00;
  243. i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
  244. ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
  245. if (ret) {
  246. printf("I2C write error (ret=%d)\n", ret);
  247. printf("Issuing soft-reset...\n");
  248. /* default handling: SOFT reset */
  249. do_reset(NULL, 0, 0, NULL);
  250. }
  251. /* Wait for power-cycle to occur... */
  252. printf("Waiting for power-cycle via uC...\n");
  253. while (1)
  254. ;
  255. } else {
  256. printf("Issuing soft-reset...\n");
  257. /* default handling: SOFT reset */
  258. do_reset(NULL, 0, 0, NULL);
  259. }
  260. }
  261. return 0;
  262. }
  263. #endif
  264. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
  265. int do_pcie_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  266. {
  267. pci_dev_t bdf;
  268. u16 ven_id, dev_id;
  269. if (argc != 3)
  270. return cmd_usage(cmdtp);
  271. ven_id = simple_strtoul(argv[1], NULL, 16);
  272. dev_id = simple_strtoul(argv[2], NULL, 16);
  273. printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
  274. ven_id, dev_id);
  275. /*
  276. * Check if the PCIe device is detected (somtimes its not available
  277. * on the PCIe bus)
  278. */
  279. bdf = pci_find_device(ven_id, dev_id, 0);
  280. if (bdf == -1) {
  281. /* PCIe device not found! */
  282. printf("Failed to find PCIe device\n");
  283. } else {
  284. /* PCIe device found! */
  285. printf("PCIe device found, resetting board...\n");
  286. /* default handling: SOFT reset */
  287. do_reset(NULL, 0, 0, NULL);
  288. }
  289. return 0;
  290. }
  291. U_BOOT_CMD(
  292. pcie, 3, 0, do_pcie_test,
  293. "Test for presence of a PCIe device",
  294. "<VendorID> <DeviceID>"
  295. );
  296. #endif