ts4800.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Savoir-faire Linux Inc.
  4. *
  5. * Derived from MX51EVK code by
  6. * Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <net.h>
  12. #include <asm/io.h>
  13. #include <asm/gpio.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/iomux-mx51.h>
  16. #include <env.h>
  17. #include <linux/delay.h>
  18. #include <linux/errno.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/arch/crm_regs.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/mach-imx/mx5_video.h>
  23. #include <mmc.h>
  24. #include <input.h>
  25. #include <fsl_esdhc_imx.h>
  26. #include <mc13892.h>
  27. #include <malloc.h>
  28. #include <netdev.h>
  29. #include <phy.h>
  30. #include "ts4800.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #ifdef CONFIG_FSL_ESDHC_IMX
  33. struct fsl_esdhc_cfg esdhc_cfg[2] = {
  34. {MMC_SDHC1_BASE_ADDR},
  35. {MMC_SDHC2_BASE_ADDR},
  36. };
  37. #endif
  38. int dram_init(void)
  39. {
  40. /* dram_init must store complete ramsize in gd->ram_size */
  41. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  42. PHYS_SDRAM_1_SIZE);
  43. return 0;
  44. }
  45. u32 get_board_rev(void)
  46. {
  47. u32 rev = get_cpu_rev();
  48. if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
  49. rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
  50. return rev;
  51. }
  52. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
  53. static void setup_iomux_uart(void)
  54. {
  55. static const iomux_v3_cfg_t uart_pads[] = {
  56. MX51_PAD_UART1_RXD__UART1_RXD,
  57. MX51_PAD_UART1_TXD__UART1_TXD,
  58. NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
  59. NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
  60. };
  61. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  62. }
  63. static void setup_iomux_fec(void)
  64. {
  65. static const iomux_v3_cfg_t fec_pads[] = {
  66. NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO,
  67. PAD_CTL_HYS |
  68. PAD_CTL_PUS_22K_UP |
  69. PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  70. MX51_PAD_EIM_EB3__FEC_RDATA1,
  71. NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS),
  72. MX51_PAD_EIM_CS3__FEC_RDATA3,
  73. MX51_PAD_NANDF_CS2__FEC_TX_ER,
  74. MX51_PAD_EIM_CS5__FEC_CRS,
  75. MX51_PAD_EIM_CS4__FEC_RX_ER,
  76. /* PAD used on TS4800 */
  77. MX51_PAD_DI2_PIN2__FEC_MDC,
  78. MX51_PAD_DISP2_DAT14__FEC_RDAT0,
  79. MX51_PAD_DISP2_DAT10__FEC_COL,
  80. MX51_PAD_DISP2_DAT11__FEC_RXCLK,
  81. MX51_PAD_DISP2_DAT15__FEC_TDAT0,
  82. MX51_PAD_DISP2_DAT6__FEC_TDAT1,
  83. MX51_PAD_DISP2_DAT7__FEC_TDAT2,
  84. MX51_PAD_DISP2_DAT8__FEC_TDAT3,
  85. MX51_PAD_DISP2_DAT9__FEC_TX_EN,
  86. MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
  87. MX51_PAD_DISP2_DAT12__FEC_RX_DV,
  88. };
  89. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  90. }
  91. #ifdef CONFIG_FSL_ESDHC_IMX
  92. int board_mmc_getcd(struct mmc *mmc)
  93. {
  94. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  95. int ret;
  96. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
  97. NO_PAD_CTRL));
  98. gpio_direction_input(IMX_GPIO_NR(1, 0));
  99. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
  100. NO_PAD_CTRL));
  101. gpio_direction_input(IMX_GPIO_NR(1, 6));
  102. if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  103. ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
  104. else
  105. ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
  106. return ret;
  107. }
  108. int board_mmc_init(struct bd_info *bis)
  109. {
  110. static const iomux_v3_cfg_t sd1_pads[] = {
  111. NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
  112. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  113. NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
  114. PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  115. NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
  116. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  117. NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
  118. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  119. NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
  120. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  121. NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
  122. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
  123. NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
  124. NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
  125. };
  126. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  127. imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
  128. return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
  129. }
  130. #endif
  131. int board_early_init_f(void)
  132. {
  133. setup_iomux_uart();
  134. setup_iomux_fec();
  135. return 0;
  136. }
  137. int board_init(void)
  138. {
  139. /* address of boot parameters */
  140. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  141. return 0;
  142. }
  143. /*
  144. * Read the MAC address from FEC's registers PALR PAUR.
  145. * User is supposed to configure these registers when MAC address is known
  146. * from another source (fuse), but on TS4800, MAC address is not fused and
  147. * the bootrom configure these registers on startup.
  148. */
  149. static int fec_get_mac_from_register(uint32_t base_addr)
  150. {
  151. unsigned char ethaddr[6];
  152. u32 reg_mac[2];
  153. int i;
  154. reg_mac[0] = in_be32(base_addr + 0xE4);
  155. reg_mac[1] = in_be32(base_addr + 0xE8);
  156. for(i = 0; i < 6; i++)
  157. ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF;
  158. if (is_valid_ethaddr(ethaddr)) {
  159. eth_env_set_enetaddr("ethaddr", ethaddr);
  160. return 0;
  161. }
  162. return -1;
  163. }
  164. #define TS4800_GPIO_FEC_PHY_RES IMX_GPIO_NR(2, 14)
  165. int board_eth_init(struct bd_info *bd)
  166. {
  167. int dev_id = -1;
  168. int phy_id = 0xFF;
  169. uint32_t addr = IMX_FEC_BASE;
  170. uint32_t base_mii;
  171. struct mii_dev *bus = NULL;
  172. struct phy_device *phydev = NULL;
  173. int ret;
  174. /* reset FEC phy */
  175. imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14);
  176. gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0);
  177. mdelay(1);
  178. gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1);
  179. mdelay(1);
  180. base_mii = addr;
  181. debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
  182. bus = fec_get_miibus(base_mii, dev_id);
  183. if (!bus)
  184. return -ENOMEM;
  185. phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII);
  186. if (!phydev) {
  187. free(bus);
  188. return -ENOMEM;
  189. }
  190. if (fec_get_mac_from_register(addr))
  191. printf("eth_init: failed to get MAC address\n");
  192. ret = fec_probe(bd, dev_id, addr, bus, phydev);
  193. if (ret) {
  194. free(phydev);
  195. free(bus);
  196. }
  197. return ret;
  198. }
  199. /*
  200. * Do not overwrite the console
  201. * Use always serial for U-Boot console
  202. */
  203. int overwrite_console(void)
  204. {
  205. return 1;
  206. }
  207. int checkboard(void)
  208. {
  209. puts("Board: TS4800\n");
  210. return 0;
  211. }
  212. void hw_watchdog_reset(void)
  213. {
  214. struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
  215. /* feed the watchdog for another 10s */
  216. writew(0x2, &wtd->feed);
  217. }
  218. void hw_watchdog_init(void)
  219. {
  220. return;
  221. }