spl.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <hang.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/ddr.h>
  11. #include <asm/arch/imx8mq_pins.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/io.h>
  14. #include <asm/mach-imx/gpio.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/mxc_i2c.h>
  17. #include <linux/delay.h>
  18. #include <errno.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <mmc.h>
  21. #include <spl.h>
  22. #include "lpddr4_timing.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define DDR_DET_1 IMX_GPIO_NR(3, 11)
  25. #define DDR_DET_2 IMX_GPIO_NR(3, 12)
  26. #define DDR_DET_3 IMX_GPIO_NR(3, 13)
  27. static iomux_v3_cfg_t const verdet_pads[] = {
  28. IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  29. IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
  30. IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
  31. IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  32. IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  33. IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  34. IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  35. };
  36. /*
  37. * DDR_DET_1 DDR_DET_2 DDR_DET_3
  38. * 0 0 1 4G LPDDR4
  39. * 1 1 1 3G LPDDR4
  40. * 1 1 0 2G LPDDR4
  41. * 1 0 1 1G LPDDR4
  42. */
  43. static void spl_dram_init(void)
  44. {
  45. struct dram_timing_info *dram_timing;
  46. u8 ddr = 0, size;
  47. imx_iomux_v3_setup_multiple_pads(verdet_pads, ARRAY_SIZE(verdet_pads));
  48. gpio_request(DDR_DET_1, "ddr_det_1");
  49. gpio_direction_input(DDR_DET_1);
  50. gpio_request(DDR_DET_2, "ddr_det_2");
  51. gpio_direction_input(DDR_DET_2);
  52. gpio_request(DDR_DET_3, "ddr_det_3");
  53. gpio_direction_input(DDR_DET_3);
  54. ddr |= !!gpio_get_value(DDR_DET_3) << 0;
  55. ddr |= !!gpio_get_value(DDR_DET_2) << 1;
  56. ddr |= !!gpio_get_value(DDR_DET_1) << 2;
  57. switch (ddr) {
  58. case 0x1:
  59. size = 4;
  60. dram_timing = &dram_timing_4gb;
  61. break;
  62. case 0x7:
  63. size = 3;
  64. dram_timing = &dram_timing_3gb;
  65. break;
  66. case 0x6:
  67. size = 2;
  68. dram_timing = &dram_timing_2gb;
  69. break;
  70. case 0x5:
  71. size = 1;
  72. dram_timing = &dram_timing_1gb;
  73. break;
  74. default:
  75. puts("Unknown DDR type!!!\n");
  76. return;
  77. }
  78. printf("%s: LPDDR4 %d GiB\n", __func__, size);
  79. ddr_init(dram_timing);
  80. writel(size, M4_BOOTROM_BASE_ADDR);
  81. }
  82. #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
  83. #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
  84. #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  85. int board_mmc_getcd(struct mmc *mmc)
  86. {
  87. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  88. int ret = 0;
  89. switch (cfg->esdhc_base) {
  90. case USDHC1_BASE_ADDR:
  91. ret = 1;
  92. break;
  93. case USDHC2_BASE_ADDR:
  94. ret = !gpio_get_value(USDHC2_CD_GPIO);
  95. return ret;
  96. }
  97. return 1;
  98. }
  99. #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
  100. PAD_CTL_FSEL2)
  101. #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
  102. static iomux_v3_cfg_t const usdhc1_pads[] = {
  103. IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  104. IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105. IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  106. IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107. IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108. IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109. IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110. IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111. IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112. IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  113. IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  114. };
  115. static iomux_v3_cfg_t const usdhc2_pads[] = {
  116. IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119. IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120. IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121. IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122. IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  123. IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  124. };
  125. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  126. {USDHC1_BASE_ADDR, 0, 8},
  127. {USDHC2_BASE_ADDR, 0, 4},
  128. };
  129. int board_mmc_init(struct bd_info *bis)
  130. {
  131. int ret;
  132. /*
  133. * According to the board_mmc_init() the following map is done:
  134. * (U-Boot device node) (Physical Port)
  135. * mmc0 USDHC1
  136. * mmc1 USDHC2
  137. */
  138. init_clk_usdhc(0);
  139. usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
  140. imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  141. gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
  142. gpio_direction_output(USDHC1_PWR_GPIO, 0);
  143. udelay(500);
  144. gpio_direction_output(USDHC1_PWR_GPIO, 1);
  145. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  146. if (ret)
  147. return ret;
  148. init_clk_usdhc(1);
  149. usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
  150. imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  151. gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
  152. gpio_direction_output(USDHC2_PWR_GPIO, 0);
  153. udelay(500);
  154. gpio_direction_output(USDHC2_PWR_GPIO, 1);
  155. return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
  156. }
  157. void spl_board_init(void)
  158. {
  159. puts("Normal Boot\n");
  160. }
  161. #ifdef CONFIG_SPL_LOAD_FIT
  162. int board_fit_config_name_match(const char *name)
  163. {
  164. /* Just empty function now - can't decide what to choose */
  165. debug("%s: %s\n", __func__, name);
  166. return 0;
  167. }
  168. #endif
  169. void board_init_f(ulong dummy)
  170. {
  171. int ret;
  172. /* Clear global data */
  173. memset((void *)gd, 0, sizeof(gd_t));
  174. arch_cpu_init();
  175. init_uart_clk(0);
  176. board_early_init_f();
  177. timer_init();
  178. preloader_console_init();
  179. /* Clear the BSS. */
  180. memset(__bss_start, 0, __bss_end - __bss_start);
  181. ret = spl_init();
  182. if (ret) {
  183. debug("spl_init() failed: %d\n", ret);
  184. hang();
  185. }
  186. enable_tzc380();
  187. /* DDR initialization */
  188. spl_dram_init();
  189. board_init_r(NULL, 0);
  190. }