tbs2910.cfg 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2017 Soeren Moch <smoch@web.de>
  4. */
  5. #define __ASSEMBLY__
  6. #include "asm/arch/crm_regs.h"
  7. #include "asm/arch/iomux.h"
  8. #include "asm/arch/mx6-ddr.h"
  9. /* image version 2 for imx6 */
  10. IMAGE_VERSION 2
  11. BOOT_FROM sd
  12. /* set the default clock gates to save power */
  13. DATA 4, CCM_CCGR0, 0x00C03F3F
  14. DATA 4, CCM_CCGR1, 0x0030FC03
  15. DATA 4, CCM_CCGR2, 0x0FFFC000
  16. DATA 4, CCM_CCGR3, 0x3FF00000
  17. DATA 4, CCM_CCGR4, 0x00FFF300
  18. DATA 4, CCM_CCGR5, 0x0F0000C3
  19. DATA 4, CCM_CCGR6, 0x000003FF
  20. /* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */
  21. DATA 4, CCM_CCOSR, 0x000000fb
  22. /* enable AXI cache for VDOA/VPU/IPU */
  23. DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
  24. /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
  25. DATA 4, MX6_IOMUXC_GPR6, 0x77177717
  26. DATA 4, MX6_IOMUXC_GPR7, 0x77177717
  27. /*
  28. * DDR3/DDR3L settings
  29. * use default 40 Ohm pad drive strength, no odt
  30. * 4x256Mx16 DDR3L-1066 7-7-7
  31. */
  32. /* disable dq pullup */
  33. DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
  34. /* disable dqs pullup */
  35. DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
  36. DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
  37. DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
  38. DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
  39. DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
  40. DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
  41. DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
  42. DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
  43. /* set ddr input mode for dq signals */
  44. DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
  45. /* set ddr input mode for dqs signals */
  46. DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
  47. /* set pad calibration type to DDR3 */
  48. DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
  49. /* ZQ calibration */
  50. DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
  51. /* dqs write delay */
  52. DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f
  53. DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f
  54. DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f
  55. DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f
  56. /* dqs read delay */
  57. DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
  58. DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
  59. DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
  60. DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
  61. DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
  62. DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
  63. DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
  64. DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
  65. /* dqs read gating control */
  66. DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300
  67. DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300
  68. DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300
  69. DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300
  70. /* start delay line calibration */
  71. DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
  72. /* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */
  73. DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
  74. /* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
  75. DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
  76. /* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */
  77. DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
  78. /* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */
  79. DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
  80. /* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */
  81. DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
  82. /* ODT timing */
  83. DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
  84. /* read odt settings, 120 Ohm */
  85. DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
  86. DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
  87. /* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */
  88. DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
  89. /* interleaved bank access (row/bank/col), 5 cycles additional read delay */
  90. DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
  91. /* 2GiByte RAM at cs0 */
  92. DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
  93. /* load mode registers of external ddr chips */
  94. DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
  95. DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
  96. DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
  97. DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
  98. /* externel chip ZQ calibration */
  99. DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
  100. /* configure and start refreshes, 8 refresh commands at 32 kHz */
  101. DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
  102. /* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */
  103. DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
  104. /* set automatic self refresh */
  105. DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
  106. /* controller configuration finished */
  107. DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000