lowlevel_init.S 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011
  4. * Matthias Weisser <weisserm@arcor.de>
  5. *
  6. * (C) Copyright 2009 DENX Software Engineering
  7. * Author: John Rigby <jrigby@gmail.com>
  8. *
  9. * Based on U-Boot and RedBoot sources for several different i.mx
  10. * platforms.
  11. */
  12. #include <asm/macro.h>
  13. #include <asm/arch/macro.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <generated/asm-offsets.h>
  16. /*
  17. * clocks
  18. */
  19. .macro init_clocks
  20. /* disable clock output */
  21. write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
  22. write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
  23. /*
  24. * enable all implemented clocks in all three
  25. * clock control registers
  26. */
  27. write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
  28. write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
  29. write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
  30. /* Devide NAND clock by 32 */
  31. write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
  32. .endm
  33. /*
  34. * sdram controller init
  35. */
  36. .macro init_lpddr
  37. ldr r0, =IMX_ESDRAMC_BASE
  38. ldr r2, =IMX_SDRAM_BANK0_BASE
  39. /*
  40. * reset SDRAM controller
  41. * then wait for initialization to complete
  42. */
  43. ldr r1, =(1 << 1) | (1 << 2)
  44. str r1, [r0, #ESDRAMC_ESDMISC]
  45. 1: ldr r3, [r0, #ESDRAMC_ESDMISC]
  46. tst r3, #(1 << 31)
  47. beq 1b
  48. ldr r1, =(1 << 2)
  49. str r1, [r0, #ESDRAMC_ESDMISC]
  50. ldr r1, =0x002a7420
  51. str r1, [r0, #ESDRAMC_ESDCFG0]
  52. /* control | precharge */
  53. ldr r1, =0x92216008
  54. str r1, [r0, #ESDRAMC_ESDCTL0]
  55. /* dram command encoded in address */
  56. str r1, [r2, #0x400]
  57. /* auto refresh */
  58. ldr r1, =0xa2216008
  59. str r1, [r0, #ESDRAMC_ESDCTL0]
  60. /* read dram twice to auto refresh */
  61. ldr r3, [r2]
  62. ldr r3, [r2]
  63. /* control | load mode */
  64. ldr r1, =0xb2216008
  65. str r1, [r0, #ESDRAMC_ESDCTL0]
  66. /* mode register of lpddram */
  67. strb r1, [r2, #0x33]
  68. /* extended mode register of lpddrram */
  69. ldr r2, =0x81000000
  70. strb r1, [r2]
  71. /* control | normal */
  72. ldr r1, =0x82216008
  73. str r1, [r0, #ESDRAMC_ESDCTL0]
  74. .endm
  75. .globl lowlevel_init
  76. lowlevel_init:
  77. init_aips
  78. init_max
  79. init_clocks
  80. init_lpddr
  81. mov pc, lr