mx6cuboxi.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. *
  7. * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
  8. *
  9. * Based on SPL code from Solidrun tree, which is:
  10. * Author: Tungyi Lin <tungyilin1127@gmail.com>
  11. *
  12. * Derived from EDM_CF_IMX6 code by TechNexion,Inc
  13. * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
  14. */
  15. #include <common.h>
  16. #include <image.h>
  17. #include <init.h>
  18. #include <log.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/imx-regs.h>
  21. #include <asm/arch/iomux.h>
  22. #include <asm/arch/mx6-pins.h>
  23. #include <asm/arch/mxc_hdmi.h>
  24. #include <env.h>
  25. #include <linux/delay.h>
  26. #include <linux/errno.h>
  27. #include <asm/gpio.h>
  28. #include <asm/mach-imx/iomux-v3.h>
  29. #include <asm/mach-imx/sata.h>
  30. #include <asm/mach-imx/video.h>
  31. #include <mmc.h>
  32. #include <fsl_esdhc_imx.h>
  33. #include <malloc.h>
  34. #include <asm/arch/crm_regs.h>
  35. #include <asm/io.h>
  36. #include <asm/arch/sys_proto.h>
  37. #include <spl.h>
  38. #include <usb.h>
  39. #include <usb/ehci-ci.h>
  40. DECLARE_GLOBAL_DATA_PTR;
  41. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  42. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  43. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  44. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  45. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  46. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  47. #define USB_H1_VBUS IMX_GPIO_NR(1, 0)
  48. enum board_type {
  49. CUBOXI = 0x00,
  50. HUMMINGBOARD = 0x01,
  51. HUMMINGBOARD2 = 0x02,
  52. UNKNOWN = 0x03,
  53. };
  54. static struct gpio_desc board_detect_desc[5];
  55. #define MEM_STRIDE 0x4000000
  56. static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
  57. {
  58. volatile u32 *addr;
  59. u32 save[64];
  60. u32 cnt;
  61. u32 size;
  62. int i = 0;
  63. /* First save the data */
  64. for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
  65. addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */
  66. sync ();
  67. save[i++] = *addr;
  68. sync ();
  69. }
  70. /* First write a signature */
  71. * (volatile u32 *)base = 0x12345678;
  72. for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
  73. * (volatile u32 *)((u32)base + size) = size;
  74. sync ();
  75. if (* (volatile u32 *)((u32)base) == size) { /* We reached the overlapping address */
  76. break;
  77. }
  78. }
  79. /* Restore the data */
  80. for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
  81. addr = (volatile u32 *)((u32)base + cnt); /* pointer arith! */
  82. sync ();
  83. *addr = save[i--];
  84. sync ();
  85. }
  86. return (size);
  87. }
  88. int dram_init(void)
  89. {
  90. u32 max_size = imx_ddr_size();
  91. gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
  92. (u32)max_size);
  93. return 0;
  94. }
  95. static iomux_v3_cfg_t const uart1_pads[] = {
  96. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  97. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  98. };
  99. static iomux_v3_cfg_t const usdhc2_pads[] = {
  100. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  101. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  102. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  103. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  104. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  105. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  106. };
  107. static iomux_v3_cfg_t const usdhc3_pads[] = {
  108. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  109. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  110. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  111. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  112. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  113. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  114. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  115. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  116. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  117. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  118. IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  119. };
  120. static iomux_v3_cfg_t const board_detect[] = {
  121. /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
  122. IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)),
  123. IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
  124. IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(UART_PAD_CTRL)),
  125. };
  126. static iomux_v3_cfg_t const som_rev_detect[] = {
  127. /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
  128. IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00 | MUX_PAD_CTRL(UART_PAD_CTRL)),
  129. IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
  130. };
  131. static void setup_iomux_uart(void)
  132. {
  133. SETUP_IOMUX_PADS(uart1_pads);
  134. }
  135. int board_mmc_get_env_dev(int devno)
  136. {
  137. return devno;
  138. }
  139. #ifdef CONFIG_VIDEO_IPUV3
  140. static void do_enable_hdmi(struct display_info_t const *dev)
  141. {
  142. imx_enable_hdmi_phy();
  143. }
  144. struct display_info_t const displays[] = {
  145. {
  146. .bus = -1,
  147. .addr = 0,
  148. .pixfmt = IPU_PIX_FMT_RGB24,
  149. .detect = detect_hdmi,
  150. .enable = do_enable_hdmi,
  151. .mode = {
  152. .name = "HDMI",
  153. /* 1024x768@60Hz (VESA)*/
  154. .refresh = 60,
  155. .xres = 1024,
  156. .yres = 768,
  157. .pixclock = 15384,
  158. .left_margin = 160,
  159. .right_margin = 24,
  160. .upper_margin = 29,
  161. .lower_margin = 3,
  162. .hsync_len = 136,
  163. .vsync_len = 6,
  164. .sync = FB_SYNC_EXT,
  165. .vmode = FB_VMODE_NONINTERLACED
  166. }
  167. }
  168. };
  169. size_t display_count = ARRAY_SIZE(displays);
  170. static int setup_display(void)
  171. {
  172. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  173. int reg;
  174. int timeout = 100000;
  175. enable_ipu_clock();
  176. imx_setup_hdmi();
  177. /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
  178. setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  179. reg = readl(&ccm->analog_pll_video);
  180. reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  181. reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
  182. reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  183. reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
  184. writel(reg, &ccm->analog_pll_video);
  185. writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
  186. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
  187. reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
  188. writel(reg, &ccm->analog_pll_video);
  189. while (timeout--)
  190. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  191. break;
  192. if (timeout < 0) {
  193. printf("Warning: video pll lock timeout!\n");
  194. return -ETIMEDOUT;
  195. }
  196. reg = readl(&ccm->analog_pll_video);
  197. reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
  198. reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
  199. writel(reg, &ccm->analog_pll_video);
  200. /* gate ipu1_di0_clk */
  201. clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  202. /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
  203. reg = readl(&ccm->chsccdr);
  204. reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
  205. MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
  206. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  207. reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
  208. (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
  209. (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  210. writel(reg, &ccm->chsccdr);
  211. /* enable ipu1_di0_clk */
  212. setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  213. return 0;
  214. }
  215. #endif /* CONFIG_VIDEO_IPUV3 */
  216. static int setup_fec(void)
  217. {
  218. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  219. int ret;
  220. ret = enable_fec_anatop_clock(0, ENET_25MHZ);
  221. if (ret)
  222. return ret;
  223. /* set gpr1[ENET_CLK_SEL] */
  224. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  225. return 0;
  226. }
  227. int board_early_init_f(void)
  228. {
  229. setup_iomux_uart();
  230. #ifdef CONFIG_CMD_SATA
  231. setup_sata();
  232. #endif
  233. setup_fec();
  234. return 0;
  235. }
  236. int board_init(void)
  237. {
  238. int ret = 0;
  239. /* address of boot parameters */
  240. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  241. #ifdef CONFIG_VIDEO_IPUV3
  242. ret = setup_display();
  243. #endif
  244. return ret;
  245. }
  246. static int request_detect_gpios(void)
  247. {
  248. int node;
  249. int ret;
  250. node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
  251. "solidrun,hummingboard-detect");
  252. if (node < 0)
  253. return -ENODEV;
  254. ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
  255. "detect-gpios", board_detect_desc,
  256. ARRAY_SIZE(board_detect_desc), GPIOD_IS_IN);
  257. return ret;
  258. }
  259. static int free_detect_gpios(void)
  260. {
  261. return gpio_free_list_nodev(board_detect_desc,
  262. ARRAY_SIZE(board_detect_desc));
  263. }
  264. static enum board_type board_type(void)
  265. {
  266. int val1, val2, val3;
  267. SETUP_IOMUX_PADS(board_detect);
  268. /*
  269. * Machine selection -
  270. * Machine val1, val2, val3
  271. * ----------------------------
  272. * HB2 x x 0
  273. * HB rev 3.x x 0 x
  274. * CBi 0 1 x
  275. * HB 1 1 x
  276. */
  277. gpio_direction_input(IMX_GPIO_NR(2, 8));
  278. val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
  279. if (val3 == 0)
  280. return HUMMINGBOARD2;
  281. gpio_direction_input(IMX_GPIO_NR(3, 4));
  282. val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
  283. if (val2 == 0)
  284. return HUMMINGBOARD;
  285. gpio_direction_input(IMX_GPIO_NR(4, 9));
  286. val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
  287. if (val1 == 0) {
  288. return CUBOXI;
  289. } else {
  290. return HUMMINGBOARD;
  291. }
  292. }
  293. static bool is_rev_15_som(void)
  294. {
  295. int val1, val2;
  296. SETUP_IOMUX_PADS(som_rev_detect);
  297. val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
  298. val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
  299. if (val1 == 1 && val2 == 0)
  300. return true;
  301. return false;
  302. }
  303. static bool has_emmc(void)
  304. {
  305. struct mmc *mmc;
  306. mmc = find_mmc_device(2);
  307. if (!mmc)
  308. return 0;
  309. return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
  310. }
  311. int checkboard(void)
  312. {
  313. request_detect_gpios();
  314. switch (board_type()) {
  315. case CUBOXI:
  316. puts("Board: MX6 Cubox-i");
  317. break;
  318. case HUMMINGBOARD:
  319. puts("Board: MX6 HummingBoard");
  320. break;
  321. case HUMMINGBOARD2:
  322. puts("Board: MX6 HummingBoard2");
  323. break;
  324. case UNKNOWN:
  325. default:
  326. puts("Board: Unknown\n");
  327. goto out;
  328. }
  329. if (is_rev_15_som())
  330. puts(" (som rev 1.5)\n");
  331. else
  332. puts("\n");
  333. free_detect_gpios();
  334. out:
  335. return 0;
  336. }
  337. /* Override the default implementation, DT model is not accurate */
  338. int show_board_info(void)
  339. {
  340. return checkboard();
  341. }
  342. int board_late_init(void)
  343. {
  344. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  345. request_detect_gpios();
  346. switch (board_type()) {
  347. case CUBOXI:
  348. env_set("board_name", "CUBOXI");
  349. break;
  350. case HUMMINGBOARD:
  351. env_set("board_name", "HUMMINGBOARD");
  352. break;
  353. case HUMMINGBOARD2:
  354. env_set("board_name", "HUMMINGBOARD2");
  355. break;
  356. case UNKNOWN:
  357. default:
  358. env_set("board_name", "CUBOXI");
  359. }
  360. if (is_mx6dq())
  361. env_set("board_rev", "MX6Q");
  362. else
  363. env_set("board_rev", "MX6DL");
  364. if (is_rev_15_som())
  365. env_set("som_rev", "V15");
  366. if (has_emmc())
  367. env_set("has_emmc", "yes");
  368. free_detect_gpios();
  369. #endif
  370. return 0;
  371. }
  372. /*
  373. * This is not a perfect match. Avoid dependency on the DM GPIO driver needed
  374. * for accurate board detection. Hummingboard2 DT is good enough for U-Boot on
  375. * all Hummingboard/Cubox-i platforms.
  376. */
  377. int board_fit_config_name_match(const char *name)
  378. {
  379. char tmp_name[36];
  380. snprintf(tmp_name, sizeof(tmp_name), "%s-hummingboard2-emmc-som-v15",
  381. is_mx6dq() ? "imx6q" : "imx6dl");
  382. return strcmp(name, tmp_name);
  383. }
  384. void board_boot_order(u32 *spl_boot_list)
  385. {
  386. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  387. unsigned int reg = readl(&psrc->sbmr1) >> 11;
  388. u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
  389. unsigned int bmode = readl(&src_base->sbmr2);
  390. /* If bmode is serial or USB phy is active, return serial */
  391. if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
  392. spl_boot_list[0] = BOOT_DEVICE_BOARD;
  393. return;
  394. }
  395. switch (boot_mode >> IMX6_BMODE_SHIFT) {
  396. case IMX6_BMODE_SD:
  397. case IMX6_BMODE_ESD:
  398. case IMX6_BMODE_MMC:
  399. case IMX6_BMODE_EMMC:
  400. /*
  401. * Upon reading BOOT_CFG register the following map is done:
  402. * Bit 11 and 12 of BOOT_CFG register can determine the current
  403. * mmc port
  404. * 0x1 SD2
  405. * 0x2 SD3
  406. */
  407. reg &= 0x3; /* Only care about bottom 2 bits */
  408. switch (reg) {
  409. case 1:
  410. SETUP_IOMUX_PADS(usdhc2_pads);
  411. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  412. break;
  413. case 2:
  414. SETUP_IOMUX_PADS(usdhc3_pads);
  415. spl_boot_list[0] = BOOT_DEVICE_MMC2;
  416. break;
  417. }
  418. break;
  419. default:
  420. /* By default use USB downloader */
  421. spl_boot_list[0] = BOOT_DEVICE_BOARD;
  422. break;
  423. }
  424. /* As a last resort, use serial downloader */
  425. spl_boot_list[1] = BOOT_DEVICE_BOARD;
  426. }
  427. #ifdef CONFIG_SPL_BUILD
  428. #include <asm/arch/mx6-ddr.h>
  429. static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
  430. .dram_sdclk_0 = 0x00020030,
  431. .dram_sdclk_1 = 0x00020030,
  432. .dram_cas = 0x00020030,
  433. .dram_ras = 0x00020030,
  434. .dram_reset = 0x000c0030,
  435. .dram_sdcke0 = 0x00003000,
  436. .dram_sdcke1 = 0x00003000,
  437. .dram_sdba2 = 0x00000000,
  438. .dram_sdodt0 = 0x00003030,
  439. .dram_sdodt1 = 0x00003030,
  440. .dram_sdqs0 = 0x00000030,
  441. .dram_sdqs1 = 0x00000030,
  442. .dram_sdqs2 = 0x00000030,
  443. .dram_sdqs3 = 0x00000030,
  444. .dram_sdqs4 = 0x00000030,
  445. .dram_sdqs5 = 0x00000030,
  446. .dram_sdqs6 = 0x00000030,
  447. .dram_sdqs7 = 0x00000030,
  448. .dram_dqm0 = 0x00020030,
  449. .dram_dqm1 = 0x00020030,
  450. .dram_dqm2 = 0x00020030,
  451. .dram_dqm3 = 0x00020030,
  452. .dram_dqm4 = 0x00020030,
  453. .dram_dqm5 = 0x00020030,
  454. .dram_dqm6 = 0x00020030,
  455. .dram_dqm7 = 0x00020030,
  456. };
  457. static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
  458. .dram_sdclk_0 = 0x00000028,
  459. .dram_sdclk_1 = 0x00000028,
  460. .dram_cas = 0x00000028,
  461. .dram_ras = 0x00000028,
  462. .dram_reset = 0x000c0028,
  463. .dram_sdcke0 = 0x00003000,
  464. .dram_sdcke1 = 0x00003000,
  465. .dram_sdba2 = 0x00000000,
  466. .dram_sdodt0 = 0x00003030,
  467. .dram_sdodt1 = 0x00003030,
  468. .dram_sdqs0 = 0x00000028,
  469. .dram_sdqs1 = 0x00000028,
  470. .dram_sdqs2 = 0x00000028,
  471. .dram_sdqs3 = 0x00000028,
  472. .dram_sdqs4 = 0x00000028,
  473. .dram_sdqs5 = 0x00000028,
  474. .dram_sdqs6 = 0x00000028,
  475. .dram_sdqs7 = 0x00000028,
  476. .dram_dqm0 = 0x00000028,
  477. .dram_dqm1 = 0x00000028,
  478. .dram_dqm2 = 0x00000028,
  479. .dram_dqm3 = 0x00000028,
  480. .dram_dqm4 = 0x00000028,
  481. .dram_dqm5 = 0x00000028,
  482. .dram_dqm6 = 0x00000028,
  483. .dram_dqm7 = 0x00000028,
  484. };
  485. static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
  486. .grp_ddr_type = 0x000C0000,
  487. .grp_ddrmode_ctl = 0x00020000,
  488. .grp_ddrpke = 0x00000000,
  489. .grp_addds = 0x00000030,
  490. .grp_ctlds = 0x00000030,
  491. .grp_ddrmode = 0x00020000,
  492. .grp_b0ds = 0x00000030,
  493. .grp_b1ds = 0x00000030,
  494. .grp_b2ds = 0x00000030,
  495. .grp_b3ds = 0x00000030,
  496. .grp_b4ds = 0x00000030,
  497. .grp_b5ds = 0x00000030,
  498. .grp_b6ds = 0x00000030,
  499. .grp_b7ds = 0x00000030,
  500. };
  501. static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  502. .grp_ddr_type = 0x000c0000,
  503. .grp_ddrmode_ctl = 0x00020000,
  504. .grp_ddrpke = 0x00000000,
  505. .grp_addds = 0x00000028,
  506. .grp_ctlds = 0x00000028,
  507. .grp_ddrmode = 0x00020000,
  508. .grp_b0ds = 0x00000028,
  509. .grp_b1ds = 0x00000028,
  510. .grp_b2ds = 0x00000028,
  511. .grp_b3ds = 0x00000028,
  512. .grp_b4ds = 0x00000028,
  513. .grp_b5ds = 0x00000028,
  514. .grp_b6ds = 0x00000028,
  515. .grp_b7ds = 0x00000028,
  516. };
  517. /* microSOM with Dual processor and 1GB memory */
  518. static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
  519. .p0_mpwldectrl0 = 0x00000000,
  520. .p0_mpwldectrl1 = 0x00000000,
  521. .p1_mpwldectrl0 = 0x00000000,
  522. .p1_mpwldectrl1 = 0x00000000,
  523. .p0_mpdgctrl0 = 0x0314031c,
  524. .p0_mpdgctrl1 = 0x023e0304,
  525. .p1_mpdgctrl0 = 0x03240330,
  526. .p1_mpdgctrl1 = 0x03180260,
  527. .p0_mprddlctl = 0x3630323c,
  528. .p1_mprddlctl = 0x3436283a,
  529. .p0_mpwrdlctl = 0x36344038,
  530. .p1_mpwrdlctl = 0x422a423c,
  531. };
  532. /* microSOM with Quad processor and 2GB memory */
  533. static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
  534. .p0_mpwldectrl0 = 0x00000000,
  535. .p0_mpwldectrl1 = 0x00000000,
  536. .p1_mpwldectrl0 = 0x00000000,
  537. .p1_mpwldectrl1 = 0x00000000,
  538. .p0_mpdgctrl0 = 0x0314031c,
  539. .p0_mpdgctrl1 = 0x023e0304,
  540. .p1_mpdgctrl0 = 0x03240330,
  541. .p1_mpdgctrl1 = 0x03180260,
  542. .p0_mprddlctl = 0x3630323c,
  543. .p1_mprddlctl = 0x3436283a,
  544. .p0_mpwrdlctl = 0x36344038,
  545. .p1_mpwrdlctl = 0x422a423c,
  546. };
  547. /* microSOM with Solo processor and 512MB memory */
  548. static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
  549. .p0_mpwldectrl0 = 0x0045004D,
  550. .p0_mpwldectrl1 = 0x003A0047,
  551. .p0_mpdgctrl0 = 0x023C0224,
  552. .p0_mpdgctrl1 = 0x02000220,
  553. .p0_mprddlctl = 0x44444846,
  554. .p0_mpwrdlctl = 0x32343032,
  555. };
  556. /* microSOM with Dual lite processor and 1GB memory */
  557. static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
  558. .p0_mpwldectrl0 = 0x0045004D,
  559. .p0_mpwldectrl1 = 0x003A0047,
  560. .p1_mpwldectrl0 = 0x001F001F,
  561. .p1_mpwldectrl1 = 0x00210035,
  562. .p0_mpdgctrl0 = 0x023C0224,
  563. .p0_mpdgctrl1 = 0x02000220,
  564. .p1_mpdgctrl0 = 0x02200220,
  565. .p1_mpdgctrl1 = 0x02040208,
  566. .p0_mprddlctl = 0x44444846,
  567. .p1_mprddlctl = 0x4042463C,
  568. .p0_mpwrdlctl = 0x32343032,
  569. .p1_mpwrdlctl = 0x36363430,
  570. };
  571. static struct mx6_ddr3_cfg mem_ddr_2g = {
  572. .mem_speed = 1600,
  573. .density = 2,
  574. .width = 16,
  575. .banks = 8,
  576. .rowaddr = 14,
  577. .coladdr = 10,
  578. .pagesz = 2,
  579. .trcd = 1375,
  580. .trcmin = 4875,
  581. .trasmin = 3500,
  582. };
  583. static struct mx6_ddr3_cfg mem_ddr_4g = {
  584. .mem_speed = 1600,
  585. .density = 4,
  586. .width = 16,
  587. .banks = 8,
  588. .rowaddr = 16,
  589. .coladdr = 10,
  590. .pagesz = 2,
  591. .trcd = 1375,
  592. .trcmin = 4875,
  593. .trasmin = 3500,
  594. };
  595. static void ccgr_init(void)
  596. {
  597. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  598. writel(0x00C03F3F, &ccm->CCGR0);
  599. writel(0x0030FC03, &ccm->CCGR1);
  600. writel(0x0FFFC000, &ccm->CCGR2);
  601. writel(0x3FF00000, &ccm->CCGR3);
  602. writel(0x00FFF300, &ccm->CCGR4);
  603. writel(0x0F0000C3, &ccm->CCGR5);
  604. writel(0x000003FF, &ccm->CCGR6);
  605. }
  606. static void spl_dram_init(int width)
  607. {
  608. struct mx6_ddr_sysinfo sysinfo = {
  609. /* width of data bus: 0=16, 1=32, 2=64 */
  610. .dsize = width / 32,
  611. /* config for full 4GB range so that get_mem_size() works */
  612. .cs_density = 32, /* 32Gb per CS */
  613. .ncs = 1, /* single chip select */
  614. .cs1_mirror = 0,
  615. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  616. .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
  617. .walat = 1, /* Write additional latency */
  618. .ralat = 5, /* Read additional latency */
  619. .mif3_mode = 3, /* Command prediction working mode */
  620. .bi_on = 1, /* Bank interleaving enabled */
  621. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  622. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  623. .ddr_type = DDR_TYPE_DDR3,
  624. .refsel = 1, /* Refresh cycles at 32KHz */
  625. .refr = 7, /* 8 refresh commands per refresh cycle */
  626. };
  627. if (is_mx6dq())
  628. mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
  629. else
  630. mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
  631. if (is_cpu_type(MXC_CPU_MX6D))
  632. mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
  633. else if (is_cpu_type(MXC_CPU_MX6Q))
  634. mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
  635. else if (is_cpu_type(MXC_CPU_MX6DL))
  636. mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
  637. else if (is_cpu_type(MXC_CPU_MX6SOLO))
  638. mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
  639. }
  640. void board_init_f(ulong dummy)
  641. {
  642. /* setup AIPS and disable watchdog */
  643. arch_cpu_init();
  644. ccgr_init();
  645. gpr_init();
  646. /* iomux and setup of i2c */
  647. board_early_init_f();
  648. /* setup GP timer */
  649. timer_init();
  650. /* UART clocks enabled and gd valid - init serial console */
  651. preloader_console_init();
  652. /* DDR initialization */
  653. if (is_cpu_type(MXC_CPU_MX6SOLO))
  654. spl_dram_init(32);
  655. else
  656. spl_dram_init(64);
  657. /* Clear the BSS. */
  658. memset(__bss_start, 0, __bss_end - __bss_start);
  659. /* load/boot image from boot device */
  660. board_init_r(NULL, 0);
  661. }
  662. #endif