tlb.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008
  4. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  5. *
  6. * Copyright 2008 Freescale Semiconductor, Inc.
  7. *
  8. * (C) Copyright 2000
  9. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10. */
  11. #include <common.h>
  12. #include <asm/mmu.h>
  13. struct fsl_e_tlb_entry tlb_table[] = {
  14. /* TLB 0 - for temp stack in cache */
  15. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  16. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  17. 0, 0, BOOKE_PAGESZ_4K, 0),
  18. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  19. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20. 0, 0, BOOKE_PAGESZ_4K, 0),
  21. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  22. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23. 0, 0, BOOKE_PAGESZ_4K, 0),
  24. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  25. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  26. 0, 0, BOOKE_PAGESZ_4K, 0),
  27. /*
  28. * TLB 1: 64M Non-cacheable, guarded
  29. * 0xfc000000 64M FLASH
  30. * Out of reset this entry is only 4K.
  31. */
  32. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
  33. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  34. 0, 1, BOOKE_PAGESZ_64M, 1),
  35. /*
  36. * TLB 2: 256M Non-cacheable, guarded
  37. * 0x80000000 256M PCI1 MEM First half
  38. */
  39. SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
  40. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  41. 0, 2, BOOKE_PAGESZ_256M, 1),
  42. /*
  43. * TLB 3: 256M Non-cacheable, guarded
  44. * 0x90000000 256M PCI1 MEM Second half
  45. */
  46. SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
  47. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  48. 0, 3, BOOKE_PAGESZ_256M, 1),
  49. #if defined(CONFIG_SYS_FPGA_BASE)
  50. /*
  51. * TLB 4: 1M Non-cacheable, guarded
  52. * 0xc0000000 1M FPGA and NAND
  53. */
  54. SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
  55. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56. 0, 4, BOOKE_PAGESZ_1M, 1),
  57. #endif
  58. /*
  59. * TLB 5: 64M Non-cacheable, guarded
  60. * 0xc8000000 16M LIME GDC framebuffer
  61. * 0xc9fc0000 256K LIME GDC MMIO
  62. * (0xcbfc0000 256K LIME GDC MMIO)
  63. * MMIO is relocatable and could be at 0xcbfc0000
  64. */
  65. SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
  66. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  67. 0, 5, BOOKE_PAGESZ_64M, 1),
  68. /*
  69. * TLB 6: 64M Non-cacheable, guarded
  70. * 0xe000_0000 1M CCSRBAR
  71. * 0xe200_0000 16M PCI1 IO
  72. */
  73. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  74. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  75. 0, 6, BOOKE_PAGESZ_64M, 1),
  76. #if !defined(CONFIG_SPD_EEPROM)
  77. /*
  78. * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
  79. * 0x00000000 512M DDR System memory
  80. * Without SPD EEPROM configured DDR, this must be setup manually.
  81. * Make sure the TLB count at the top of this table is correct.
  82. * Likely it needs to be increased by two for these entries.
  83. */
  84. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  85. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  86. 0, 7, BOOKE_PAGESZ_256M, 1),
  87. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
  88. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  89. 0, 8, BOOKE_PAGESZ_256M, 1),
  90. #endif
  91. };
  92. int num_tlb_entries = ARRAY_SIZE(tlb_table);