socrates.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008
  4. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  5. *
  6. * Copyright 2004 Freescale Semiconductor.
  7. * (C) Copyright 2002,2003, Motorola Inc.
  8. * Xianghua Xiao, (X.Xiao@motorola.com)
  9. *
  10. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11. */
  12. #include <common.h>
  13. #include <clock_legacy.h>
  14. #include <env.h>
  15. #include <init.h>
  16. #include <pci.h>
  17. #include <uuid.h>
  18. #include <asm/processor.h>
  19. #include <asm/immap_85xx.h>
  20. #include <ioports.h>
  21. #include <flash.h>
  22. #include <linux/delay.h>
  23. #include <linux/libfdt.h>
  24. #include <fdt_support.h>
  25. #include <asm/io.h>
  26. #include <i2c.h>
  27. #include <mb862xx.h>
  28. #include <video_fb.h>
  29. #include "upm_table.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. extern flash_info_t flash_info[]; /* FLASH chips info */
  32. extern GraphicDevice mb862xx;
  33. void local_bus_init (void);
  34. ulong flash_get_size (ulong base, int banknum);
  35. int checkboard (void)
  36. {
  37. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  38. char buf[64];
  39. int f;
  40. int i = env_get_f("serial#", buf, sizeof(buf));
  41. #ifdef CONFIG_PCI
  42. char *src;
  43. #endif
  44. puts("Board: Socrates");
  45. if (i > 0) {
  46. puts(", serial# ");
  47. puts(buf);
  48. }
  49. putc('\n');
  50. #if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
  51. /* Check the PCI_clk sel bit */
  52. if (in_be32(&gur->porpllsr) & (1<<15)) {
  53. src = "SYSCLK";
  54. f = CONFIG_SYS_CLK_FREQ;
  55. } else {
  56. src = "PCI_CLK";
  57. f = CONFIG_PCI_CLK_FREQ;
  58. }
  59. printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
  60. #else
  61. printf ("PCI1: disabled\n");
  62. #endif
  63. /*
  64. * Initialize local bus.
  65. */
  66. local_bus_init ();
  67. return 0;
  68. }
  69. int misc_init_r (void)
  70. {
  71. /*
  72. * Adjust flash start and offset to detected values
  73. */
  74. gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  75. gd->bd->bi_flashoffset = 0;
  76. /*
  77. * Check if boot FLASH isn't max size
  78. */
  79. if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
  80. set_lbc_or(0, gd->bd->bi_flashstart |
  81. (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
  82. set_lbc_br(0, gd->bd->bi_flashstart |
  83. (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
  84. /*
  85. * Re-check to get correct base address
  86. */
  87. flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
  88. }
  89. /*
  90. * Check if only one FLASH bank is available
  91. */
  92. if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
  93. set_lbc_or(1, 0);
  94. set_lbc_br(1, 0);
  95. /*
  96. * Re-do flash protection upon new addresses
  97. */
  98. flash_protect(FLAG_PROTECT_CLEAR,
  99. gd->bd->bi_flashstart, 0xffffffff,
  100. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  101. /* Monitor protection ON by default */
  102. flash_protect(FLAG_PROTECT_SET,
  103. CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
  104. monitor_flash_len - 1,
  105. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  106. /* Environment protection ON by default */
  107. flash_protect(FLAG_PROTECT_SET,
  108. CONFIG_ENV_ADDR,
  109. CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
  110. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  111. /* Redundant environment protection ON by default */
  112. flash_protect(FLAG_PROTECT_SET,
  113. CONFIG_ENV_ADDR_REDUND,
  114. CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
  115. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  116. }
  117. #if defined(CONFIG_DM_PCI)
  118. pci_init();
  119. #endif
  120. return 0;
  121. }
  122. /*
  123. * Initialize Local Bus
  124. */
  125. void local_bus_init (void)
  126. {
  127. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  128. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  129. sys_info_t sysinfo;
  130. uint clkdiv;
  131. uint lbc_mhz;
  132. uint lcrr = CONFIG_SYS_LBC_LCRR;
  133. get_sys_info (&sysinfo);
  134. clkdiv = lbc->lcrr & LCRR_CLKDIV;
  135. lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
  136. /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
  137. if (lbc_mhz >= 66)
  138. lcrr &= ~LCRR_DBYP; /* DLL Enabled */
  139. else
  140. lcrr |= LCRR_DBYP; /* DLL Bypass */
  141. out_be32 (&lbc->lcrr, lcrr);
  142. asm ("sync;isync;msync");
  143. out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
  144. out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
  145. out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
  146. out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
  147. /* Init UPMA for FPGA access */
  148. out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
  149. upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
  150. /* Init UPMB for Lime controller access */
  151. out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
  152. upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
  153. }
  154. #ifdef CONFIG_BOARD_EARLY_INIT_R
  155. int board_early_init_r (void)
  156. {
  157. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  158. /* set and reset the GPIO pin 2 which will reset the W83782G chip */
  159. out_8((unsigned char*)&gur->gpoutdr, 0x3F );
  160. out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
  161. udelay(200);
  162. out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
  163. return (0);
  164. }
  165. #endif /* CONFIG_BOARD_EARLY_INIT_R */
  166. #ifdef CONFIG_OF_BOARD_SETUP
  167. int ft_board_setup(void *blob, struct bd_info *bd)
  168. {
  169. u32 val[12];
  170. int rc, i = 0;
  171. ft_cpu_setup(blob, bd);
  172. /* Fixup NOR FLASH mapping */
  173. val[i++] = 0; /* chip select number */
  174. val[i++] = 0; /* always 0 */
  175. val[i++] = gd->bd->bi_flashstart;
  176. val[i++] = gd->bd->bi_flashsize;
  177. #if defined(CONFIG_VIDEO_MB862xx)
  178. if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
  179. /* Fixup LIME mapping */
  180. val[i++] = 2; /* chip select number */
  181. val[i++] = 0; /* always 0 */
  182. val[i++] = CONFIG_SYS_LIME_BASE;
  183. val[i++] = CONFIG_SYS_LIME_SIZE;
  184. }
  185. #endif
  186. /* Fixup FPGA mapping */
  187. val[i++] = 3; /* chip select number */
  188. val[i++] = 0; /* always 0 */
  189. val[i++] = CONFIG_SYS_FPGA_BASE;
  190. val[i++] = CONFIG_SYS_FPGA_SIZE;
  191. rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
  192. val, i * sizeof(u32), 1);
  193. if (rc)
  194. printf("Unable to update localbus ranges, err=%s\n",
  195. fdt_strerror(rc));
  196. return 0;
  197. }
  198. #endif /* CONFIG_OF_BOARD_SETUP */
  199. #if defined(CONFIG_OF_SEPARATE)
  200. void *board_fdt_blob_setup(void)
  201. {
  202. void *fw_dtb;
  203. fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
  204. if (fdt_magic(fw_dtb) != FDT_MAGIC) {
  205. printf("DTB is not passed via %x\n", (u32)fw_dtb);
  206. return NULL;
  207. }
  208. return fw_dtb;
  209. }
  210. #endif
  211. int get_serial_clock(void)
  212. {
  213. return 333333330;
  214. }