sksimx6.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/video.h>
  18. #include <mmc.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <asm/arch/crm_regs.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <spl.h>
  24. #include <netdev.h>
  25. #include <miiphy.h>
  26. #include <micrel.h>
  27. #include <common.h>
  28. #include <malloc.h>
  29. #include <fuse.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  32. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  33. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  34. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  35. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  36. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  38. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  39. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  40. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  41. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  42. static iomux_v3_cfg_t const uart1_pads[] = {
  43. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  44. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  45. };
  46. static iomux_v3_cfg_t const gpios_pads[] = {
  47. IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  48. };
  49. static iomux_v3_cfg_t const usdhc2_pads[] = {
  50. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  51. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  52. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  53. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  54. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  55. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  56. IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
  57. };
  58. static iomux_v3_cfg_t const enet_pads[] = {
  59. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  72. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  74. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  76. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77. IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  78. };
  79. iomux_v3_cfg_t const enet_pads1[] = {
  80. /* pin 35 - 1 (PHY_AD2) on reset */
  81. IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  82. /* pin 32 - 1 - (MODE0) all */
  83. IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84. /* pin 31 - 1 - (MODE1) all */
  85. IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86. /* pin 28 - 1 - (MODE2) all */
  87. IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88. /* pin 27 - 1 - (MODE3) all */
  89. IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  91. IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92. /* pin 42 PHY nRST */
  93. IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94. };
  95. static int mx6_rgmii_rework(struct phy_device *phydev)
  96. {
  97. /* min rx data delay */
  98. ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
  99. 0x0);
  100. /* min tx data delay */
  101. ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
  102. 0x0);
  103. /* max rx/tx clock delay, min rx/tx control */
  104. ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
  105. 0xf0f0);
  106. return 0;
  107. }
  108. int board_phy_config(struct phy_device *phydev)
  109. {
  110. mx6_rgmii_rework(phydev);
  111. if (phydev->drv->config)
  112. return phydev->drv->config(phydev);
  113. return 0;
  114. }
  115. #define ENET_NRST IMX_GPIO_NR(1, 25)
  116. void setup_iomux_enet(void)
  117. {
  118. SETUP_IOMUX_PADS(enet_pads);
  119. }
  120. int board_eth_init(struct bd_info *bis)
  121. {
  122. uint32_t base = IMX_FEC_BASE;
  123. struct mii_dev *bus = NULL;
  124. struct phy_device *phydev = NULL;
  125. int ret;
  126. setup_iomux_enet();
  127. bus = fec_get_miibus(base, -1);
  128. if (!bus)
  129. return -EINVAL;
  130. /* scan phy */
  131. phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
  132. PHY_INTERFACE_MODE_RGMII);
  133. if (!phydev) {
  134. ret = -EINVAL;
  135. goto free_bus;
  136. }
  137. ret = fec_probe(bis, -1, base, bus, phydev);
  138. if (ret)
  139. goto free_phydev;
  140. return 0;
  141. free_phydev:
  142. free(phydev);
  143. free_bus:
  144. free(bus);
  145. return ret;
  146. }
  147. int board_early_init_f(void)
  148. {
  149. SETUP_IOMUX_PADS(uart1_pads);
  150. return 0;
  151. }
  152. int board_init(void)
  153. {
  154. /* Address of boot parameters */
  155. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  156. /* Take in reset the ATMega processor */
  157. SETUP_IOMUX_PADS(gpios_pads);
  158. gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  159. return 0;
  160. }
  161. int dram_init(void)
  162. {
  163. gd->ram_size = imx_ddr_size();
  164. return 0;
  165. }
  166. struct fsl_esdhc_cfg usdhc_cfg[1] = {
  167. {USDHC2_BASE_ADDR, 0},
  168. };
  169. #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0)
  170. int board_mmc_getcd(struct mmc *mmc)
  171. {
  172. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  173. int ret = 0;
  174. if (cfg->esdhc_base == USDHC2_BASE_ADDR)
  175. ret = 1;
  176. return ret;
  177. }
  178. int board_mmc_init(struct bd_info *bis)
  179. {
  180. int ret;
  181. SETUP_IOMUX_PADS(usdhc2_pads);
  182. gpio_direction_input(USDHC2_CD_GPIO);
  183. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  184. usdhc_cfg[0].max_bus_width = 4;
  185. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  186. if (ret) {
  187. printf("Warning: failed to initialize mmc dev \n");
  188. return ret;
  189. }
  190. return 0;
  191. }
  192. #if defined(CONFIG_SPL_BUILD)
  193. #include <asm/arch/mx6-ddr.h>
  194. /*
  195. * Driving strength:
  196. * 0x30 == 40 Ohm
  197. * 0x28 == 48 Ohm
  198. */
  199. #define IMX6SDL_DRIVE_STRENGTH 0x230
  200. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  201. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  202. .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  203. .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  204. .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  205. .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  206. .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  207. .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  208. .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  209. .dram_sdba2 = 0x00000000,
  210. .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  211. .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  212. .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  213. .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  214. .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  215. .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  216. .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  217. .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  218. .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  219. .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  220. .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  221. .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  222. .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  223. .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  224. .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  225. .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  226. .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  227. .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  228. };
  229. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  230. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  231. .grp_ddr_type = 0x000c0000,
  232. .grp_ddrmode_ctl = 0x00020000,
  233. .grp_ddrpke = 0x00000000,
  234. .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  235. .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  236. .grp_ddrmode = 0x00020000,
  237. .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  238. .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  239. .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  240. .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  241. .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  242. .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  243. .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  244. .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  245. };
  246. /* MT41K128M16JT-125 */
  247. static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  248. /* quad = 1066, duallite = 800 */
  249. .mem_speed = 1066,
  250. .density = 2,
  251. .width = 16,
  252. .banks = 8,
  253. .rowaddr = 14,
  254. .coladdr = 10,
  255. .pagesz = 2,
  256. .trcd = 1375,
  257. .trcmin = 4875,
  258. .trasmin = 3500,
  259. .SRT = 0,
  260. };
  261. static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
  262. .p0_mpwldectrl0 = 0x0043004E,
  263. .p0_mpwldectrl1 = 0x003D003F,
  264. .p1_mpwldectrl0 = 0x00230021,
  265. .p1_mpwldectrl1 = 0x0028003E,
  266. .p0_mpdgctrl0 = 0x42580250,
  267. .p0_mpdgctrl1 = 0x0238023C,
  268. .p1_mpdgctrl0 = 0x422C0238,
  269. .p1_mpdgctrl1 = 0x02180228,
  270. .p0_mprddlctl = 0x44464A46,
  271. .p1_mprddlctl = 0x44464A42,
  272. .p0_mpwrdlctl = 0x36343236,
  273. .p1_mpwrdlctl = 0x36343230,
  274. };
  275. /* DDR 64bit 1GB */
  276. static struct mx6_ddr_sysinfo mem_qdl = {
  277. .dsize = 2,
  278. .cs1_mirror = 0,
  279. /* config for full 4GB range so that get_mem_size() works */
  280. .cs_density = 32,
  281. .ncs = 1,
  282. .bi_on = 1,
  283. .rtt_nom = 1,
  284. .rtt_wr = 1,
  285. .ralat = 5,
  286. .walat = 0,
  287. .mif3_mode = 3,
  288. .rst_to_cke = 0x23,
  289. .sde_to_rst = 0x10,
  290. .refsel = 1, /* Refresh cycles at 32KHz */
  291. .refr = 7, /* 8 refresh commands per refresh cycle */
  292. };
  293. static void ccgr_init(void)
  294. {
  295. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  296. /* set the default clock gate to save power */
  297. writel(0x00C03F3F, &ccm->CCGR0);
  298. writel(0x0030FC03, &ccm->CCGR1);
  299. writel(0x0FFFC000, &ccm->CCGR2);
  300. writel(0x3FF00000, &ccm->CCGR3);
  301. writel(0x00FFF300, &ccm->CCGR4);
  302. writel(0xFFFFFFFF, &ccm->CCGR5);
  303. writel(0x000003FF, &ccm->CCGR6);
  304. }
  305. static void spl_dram_init(void)
  306. {
  307. if (is_cpu_type(MXC_CPU_MX6DL)) {
  308. mt41k128m16jt_125.mem_speed = 800;
  309. mem_qdl.rtt_nom = 1;
  310. mem_qdl.rtt_wr = 1;
  311. mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  312. mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
  313. } else {
  314. printf("Wrong CPU for this board\n");
  315. return;
  316. }
  317. udelay(100);
  318. #ifdef CONFIG_MX6_DDRCAL
  319. /* Perform DDR DRAM calibration */
  320. mmdc_do_write_level_calibration(&mem_qdl);
  321. mmdc_do_dqs_calibration(&mem_qdl);
  322. #endif
  323. }
  324. static void check_bootcfg(void)
  325. {
  326. u32 val5, val6;
  327. fuse_sense(0, 5, &val5);
  328. fuse_sense(0, 6, &val6);
  329. /* Check if boot from MMC */
  330. if (val6 & 0x10) {
  331. puts("BT_FUSE_SEL already fused, will do nothing\n");
  332. return;
  333. }
  334. fuse_prog(0, 5, 0x00000840);
  335. /* BT_FUSE_SEL */
  336. fuse_prog(0, 6, 0x00000010);
  337. do_reset(NULL, 0, 0, NULL);
  338. }
  339. void board_init_f(ulong dummy)
  340. {
  341. ccgr_init();
  342. /* setup AIPS and disable watchdog */
  343. arch_cpu_init();
  344. gpr_init();
  345. /* iomux */
  346. board_early_init_f();
  347. /* setup GP timer */
  348. timer_init();
  349. /* UART clocks enabled and gd valid - init serial console */
  350. preloader_console_init();
  351. /* DDR initialization */
  352. spl_dram_init();
  353. /* Set fuses for new boards and reboot if not set */
  354. check_bootcfg();
  355. /* Clear the BSS. */
  356. memset(__bss_start, 0, __bss_end - __bss_start);
  357. /* load/boot image from boot device */
  358. board_init_r(NULL, 0);
  359. }
  360. #endif