smartweb.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * Achim Ehrlich <aehrlich@taskit.de>
  8. * taskit GmbH <www.taskit.de>
  9. *
  10. * (C) Copyright 2012-
  11. * Markus Hubig <mhubig@imko.de>
  12. * IMKO GmbH <www.imko.de>
  13. * (C) Copyright 2014
  14. * Heiko Schocher <hs@denx.de>
  15. * DENX Software Engineering GmbH
  16. */
  17. #include <common.h>
  18. #include <dm.h>
  19. #include <init.h>
  20. #include <net.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/at91sam9_sdramc.h>
  23. #include <asm/arch/at91sam9260_matrix.h>
  24. #include <asm/arch/at91sam9_smc.h>
  25. #include <asm/arch/at91_common.h>
  26. #include <asm/arch/atmel_serial.h>
  27. #include <asm/arch/at91_spi.h>
  28. #include <spi.h>
  29. #include <asm/arch/clk.h>
  30. #include <asm/arch/gpio.h>
  31. #include <asm/gpio.h>
  32. #include <watchdog.h>
  33. # include <net.h>
  34. #ifndef CONFIG_DM_ETH
  35. # include <netdev.h>
  36. #endif
  37. #include <g_dnl.h>
  38. DECLARE_GLOBAL_DATA_PTR;
  39. static void smartweb_request_gpio(void)
  40. {
  41. gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
  42. gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
  43. gpio_request(AT91_PIN_PA26, "ena PHY");
  44. }
  45. static void smartweb_nand_hw_init(void)
  46. {
  47. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  48. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  49. unsigned long csa;
  50. /* Assign CS3 to NAND/SmartMedia Interface */
  51. csa = readl(&matrix->ebicsa);
  52. csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  53. writel(csa, &matrix->ebicsa);
  54. /* Configure SMC CS3 for NAND/SmartMedia */
  55. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  56. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  57. &smc->cs[3].setup);
  58. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  59. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  60. &smc->cs[3].pulse);
  61. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  62. &smc->cs[3].cycle);
  63. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  64. AT91_SMC_MODE_TDF_CYCLE(2),
  65. &smc->cs[3].mode);
  66. /* Configure RDY/BSY */
  67. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  68. /* Enable NandFlash */
  69. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  70. }
  71. static void smartweb_macb_hw_init(void)
  72. {
  73. struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  74. /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
  75. at91_set_gpio_output(AT91_PIN_PA26, 0);
  76. /*
  77. * Disable pull-up on:
  78. * RXDV (PA17) => PHY normal mode (not Test mode)
  79. * ERX0 (PA14) => PHY ADDR0
  80. * ERX1 (PA15) => PHY ADDR1
  81. * ERX2 (PA25) => PHY ADDR2
  82. * ERX3 (PA26) => PHY ADDR3
  83. * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
  84. *
  85. * PHY has internal pull-down
  86. */
  87. writel(pin_to_mask(AT91_PIN_PA14) |
  88. pin_to_mask(AT91_PIN_PA15) |
  89. pin_to_mask(AT91_PIN_PA17) |
  90. pin_to_mask(AT91_PIN_PA25) |
  91. pin_to_mask(AT91_PIN_PA26) |
  92. pin_to_mask(AT91_PIN_PA28) |
  93. pin_to_mask(AT91_PIN_PA29),
  94. &pioa->pudr);
  95. at91_phy_reset();
  96. /* Re-enable pull-up */
  97. writel(pin_to_mask(AT91_PIN_PA14) |
  98. pin_to_mask(AT91_PIN_PA15) |
  99. pin_to_mask(AT91_PIN_PA17) |
  100. pin_to_mask(AT91_PIN_PA25) |
  101. pin_to_mask(AT91_PIN_PA26) |
  102. pin_to_mask(AT91_PIN_PA28) |
  103. pin_to_mask(AT91_PIN_PA29),
  104. &pioa->puer);
  105. /* Initialize EMAC=MACB hardware */
  106. at91_macb_hw_init();
  107. }
  108. #ifdef CONFIG_USB_GADGET_AT91
  109. #include <linux/usb/at91_udc.h>
  110. void at91_udp_hw_init(void)
  111. {
  112. /* Enable PLLB */
  113. at91_pllb_clk_enable(get_pllb_init());
  114. /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
  115. at91_periph_clk_enable(ATMEL_ID_UDP);
  116. at91_system_clk_enable(AT91SAM926x_PMC_UDP);
  117. }
  118. struct at91_udc_data board_udc_data = {
  119. .baseaddr = ATMEL_BASE_UDP0,
  120. };
  121. #endif
  122. int board_early_init_f(void)
  123. {
  124. /* enable this here, as we have SPL without serial support */
  125. at91_seriald_hw_init();
  126. smartweb_request_gpio();
  127. return 0;
  128. }
  129. int board_init(void)
  130. {
  131. smartweb_request_gpio();
  132. /* power LED red */
  133. at91_set_gpio_output(AT91_PIN_PC6, 0);
  134. at91_set_gpio_output(AT91_PIN_PC7, 1);
  135. /* alarm LED off */
  136. at91_set_gpio_output(AT91_PIN_PC8, 0);
  137. at91_set_gpio_output(AT91_PIN_PC9, 0);
  138. /* prog LED red */
  139. at91_set_gpio_output(AT91_PIN_PC10, 0);
  140. at91_set_gpio_output(AT91_PIN_PC11, 1);
  141. #ifdef CONFIG_USB_GADGET_AT91
  142. at91_udp_hw_init();
  143. at91_udc_probe(&board_udc_data);
  144. #endif
  145. /* Adress of boot parameters */
  146. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  147. smartweb_nand_hw_init();
  148. smartweb_macb_hw_init();
  149. return 0;
  150. }
  151. int dram_init(void)
  152. {
  153. gd->ram_size = get_ram_size(
  154. (void *)CONFIG_SYS_SDRAM_BASE,
  155. CONFIG_SYS_SDRAM_SIZE);
  156. return 0;
  157. }
  158. #ifndef CONFIG_DM_ETH
  159. #ifdef CONFIG_MACB
  160. int board_eth_init(struct bd_info *bis)
  161. {
  162. return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
  163. }
  164. #endif /* CONFIG_MACB */
  165. #endif
  166. #if defined(CONFIG_SPL_BUILD)
  167. #include <spl.h>
  168. #include <nand.h>
  169. #include <spi_flash.h>
  170. void matrix_init(void)
  171. {
  172. struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  173. writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
  174. | AT91_MATRIX_SLOT_CYCLE_(0x40),
  175. &mat->scfg[3]);
  176. }
  177. void at91_spl_board_init(void)
  178. {
  179. smartweb_request_gpio();
  180. /* power LED orange */
  181. at91_set_gpio_output(AT91_PIN_PC6, 1);
  182. at91_set_gpio_output(AT91_PIN_PC7, 1);
  183. /* alarm LED orange */
  184. at91_set_gpio_output(AT91_PIN_PC8, 1);
  185. at91_set_gpio_output(AT91_PIN_PC9, 1);
  186. /* prog LED red */
  187. at91_set_gpio_output(AT91_PIN_PC10, 0);
  188. at91_set_gpio_output(AT91_PIN_PC11, 1);
  189. smartweb_nand_hw_init();
  190. at91_set_gpio_input(AT91_PIN_PA28, 1);
  191. at91_set_gpio_input(AT91_PIN_PA29, 1);
  192. /* check if both button are pressed */
  193. if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
  194. at91_get_gpio_value(AT91_PIN_PA29) == 0) {
  195. smartweb_nand_hw_init();
  196. nand_init();
  197. spl_nand_erase_one(0, 0);
  198. }
  199. }
  200. #define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
  201. | AT91_SDRAMC_CAS_2 \
  202. | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
  203. | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
  204. | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
  205. | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))
  206. void mem_init(void)
  207. {
  208. struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  209. struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
  210. struct sdramc_reg setting;
  211. setting.cr = SDRAM_BASE_CONF;
  212. setting.mdr = AT91_SDRAMC_MD_SDRAM;
  213. setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
  214. /*
  215. * I write here directly in this register, because this
  216. * approach is smaller than calling at91_set_a_periph() in a
  217. * for loop. This saved me 96 bytes.
  218. */
  219. writel(0xffff0000, &port->pdr);
  220. writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
  221. sdramc_initialize(ATMEL_BASE_CS1, &setting);
  222. }
  223. #endif
  224. int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  225. {
  226. g_dnl_set_serialnumber("1");
  227. return 0;
  228. }