board.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for TI AM335X based rut board
  4. * (C) Copyright 2013 Siemens Schweiz AG
  5. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * Based on:
  8. * u-boot:/board/ti/am335x/board.c
  9. *
  10. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  11. */
  12. #include <common.h>
  13. #include <env.h>
  14. #include <errno.h>
  15. #include <init.h>
  16. #include <malloc.h>
  17. #include <net.h>
  18. #include <spi.h>
  19. #include <spl.h>
  20. #include <asm/arch/cpu.h>
  21. #include <asm/arch/hardware.h>
  22. #include <asm/arch/omap.h>
  23. #include <asm/arch/ddr_defs.h>
  24. #include <asm/arch/clock.h>
  25. #include <asm/arch/gpio.h>
  26. #include <asm/arch/mmc_host_def.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <asm/io.h>
  29. #include <asm/emif.h>
  30. #include <asm/gpio.h>
  31. #include <i2c.h>
  32. #include <miiphy.h>
  33. #include <cpsw.h>
  34. #include <video.h>
  35. #include <watchdog.h>
  36. #include <linux/delay.h>
  37. #include "board.h"
  38. #include "../common/factoryset.h"
  39. #include "../../../drivers/video/da8xx-fb.h"
  40. /*
  41. * Read header information from EEPROM into global structure.
  42. */
  43. static int read_eeprom(void)
  44. {
  45. return 0;
  46. }
  47. #ifdef CONFIG_SPL_BUILD
  48. static void board_init_ddr(void)
  49. {
  50. struct emif_regs rut_ddr3_emif_reg_data = {
  51. .sdram_config = 0x61C04AB2,
  52. .sdram_tim1 = 0x0888A39B,
  53. .sdram_tim2 = 0x26337FDA,
  54. .sdram_tim3 = 0x501F830F,
  55. .emif_ddr_phy_ctlr_1 = 0x6,
  56. .zq_config = 0x50074BE4,
  57. .ref_ctrl = 0x93B,
  58. };
  59. struct ddr_data rut_ddr3_data = {
  60. .datardsratio0 = 0x3b,
  61. .datawdsratio0 = 0x85,
  62. .datafwsratio0 = 0x100,
  63. .datawrsratio0 = 0xc1,
  64. };
  65. struct cmd_control rut_ddr3_cmd_ctrl_data = {
  66. .cmd0csratio = 0x40,
  67. .cmd0iclkout = 1,
  68. .cmd1csratio = 0x40,
  69. .cmd1iclkout = 1,
  70. .cmd2csratio = 0x40,
  71. .cmd2iclkout = 1,
  72. };
  73. const struct ctrl_ioregs ioregs = {
  74. .cm0ioctl = RUT_IOCTRL_VAL,
  75. .cm1ioctl = RUT_IOCTRL_VAL,
  76. .cm2ioctl = RUT_IOCTRL_VAL,
  77. .dt0ioctl = RUT_IOCTRL_VAL,
  78. .dt1ioctl = RUT_IOCTRL_VAL,
  79. };
  80. config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
  81. &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
  82. }
  83. static int request_and_pulse_reset(int gpio, const char *name)
  84. {
  85. int ret;
  86. const int delay_us = 2000; /* 2ms */
  87. ret = gpio_request(gpio, name);
  88. if (ret < 0) {
  89. printf("%s: Unable to request %s\n", __func__, name);
  90. goto err;
  91. }
  92. ret = gpio_direction_output(gpio, 0);
  93. if (ret < 0) {
  94. printf("%s: Unable to set %s as output\n", __func__, name);
  95. goto err_free_gpio;
  96. }
  97. udelay(delay_us);
  98. gpio_set_value(gpio, 1);
  99. return 0;
  100. err_free_gpio:
  101. gpio_free(gpio);
  102. err:
  103. return ret;
  104. }
  105. #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
  106. #define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
  107. #define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
  108. #define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
  109. #define REQUEST_AND_PULSE_RESET(N) \
  110. request_and_pulse_reset(N, #N);
  111. static void spl_siemens_board_init(void)
  112. {
  113. REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
  114. REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
  115. REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
  116. }
  117. #endif /* if def CONFIG_SPL_BUILD */
  118. #if defined(CONFIG_DRIVER_TI_CPSW)
  119. static void cpsw_control(int enabled)
  120. {
  121. /* VTP can be added here */
  122. return;
  123. }
  124. static struct cpsw_slave_data cpsw_slaves[] = {
  125. {
  126. .slave_reg_ofs = 0x208,
  127. .sliver_reg_ofs = 0xd80,
  128. .phy_addr = 1,
  129. .phy_if = PHY_INTERFACE_MODE_RMII,
  130. },
  131. {
  132. .slave_reg_ofs = 0x308,
  133. .sliver_reg_ofs = 0xdc0,
  134. .phy_addr = 0,
  135. .phy_if = PHY_INTERFACE_MODE_RMII,
  136. },
  137. };
  138. static struct cpsw_platform_data cpsw_data = {
  139. .mdio_base = CPSW_MDIO_BASE,
  140. .cpsw_base = CPSW_BASE,
  141. .mdio_div = 0xff,
  142. .channels = 8,
  143. .cpdma_reg_ofs = 0x800,
  144. .slaves = 1,
  145. .slave_data = cpsw_slaves,
  146. .ale_reg_ofs = 0xd00,
  147. .ale_entries = 1024,
  148. .host_port_reg_ofs = 0x108,
  149. .hw_stats_reg_ofs = 0x900,
  150. .bd_ram_ofs = 0x2000,
  151. .mac_control = (1 << 5),
  152. .control = cpsw_control,
  153. .host_port_num = 0,
  154. .version = CPSW_CTRL_VERSION_2,
  155. };
  156. #if defined(CONFIG_DRIVER_TI_CPSW) || \
  157. (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
  158. int board_eth_init(struct bd_info *bis)
  159. {
  160. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  161. int n = 0;
  162. int rv;
  163. #ifndef CONFIG_SPL_BUILD
  164. factoryset_env_set();
  165. #endif
  166. /* Set rgmii mode and enable rmii clock to be sourced from chip */
  167. writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
  168. rv = cpsw_register(&cpsw_data);
  169. if (rv < 0)
  170. printf("Error %d registering CPSW switch\n", rv);
  171. else
  172. n += rv;
  173. return n;
  174. }
  175. #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
  176. #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
  177. #if defined(CONFIG_HW_WATCHDOG)
  178. static bool hw_watchdog_init_done;
  179. static int hw_watchdog_trigger_level;
  180. void hw_watchdog_reset(void)
  181. {
  182. if (!hw_watchdog_init_done)
  183. return;
  184. hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
  185. gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
  186. }
  187. void hw_watchdog_init(void)
  188. {
  189. gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
  190. gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
  191. hw_watchdog_reset();
  192. hw_watchdog_init_done = 1;
  193. }
  194. #endif /* defined(CONFIG_HW_WATCHDOG) */
  195. #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
  196. static struct da8xx_panel lcd_panels[] = {
  197. /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
  198. [0] = {
  199. .name = "KWH043MC17-F01",
  200. .width = 480,
  201. .height = 800,
  202. .hfp = 50, /* no spec, "don't care" values */
  203. .hbp = 50,
  204. .hsw = 50,
  205. .vfp = 50,
  206. .vbp = 50,
  207. .vsw = 50,
  208. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  209. .invert_pxl_clk = 1,
  210. },
  211. /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
  212. [1] = {
  213. .name = "KWH043ST20-F01",
  214. .width = 480,
  215. .height = 800,
  216. .hfp = 50, /* no spec, "don't care" values */
  217. .hbp = 50,
  218. .hsw = 50,
  219. .vfp = 50,
  220. .vbp = 50,
  221. .vsw = 50,
  222. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  223. .invert_pxl_clk = 1,
  224. },
  225. /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
  226. [2] = {
  227. .name = "MI0430VT-1",
  228. .width = 480,
  229. .height = 800,
  230. .hfp = 50, /* no spec, "don't care" values */
  231. .hbp = 50,
  232. .hsw = 50,
  233. .vfp = 50,
  234. .vbp = 50,
  235. .vsw = 50,
  236. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  237. .invert_pxl_clk = 1,
  238. },
  239. };
  240. static const struct display_panel disp_panels[] = {
  241. [0] = {
  242. WVGA,
  243. 16, /* RGB 888 */
  244. 16,
  245. COLOR_ACTIVE,
  246. },
  247. [1] = {
  248. WVGA,
  249. 16, /* RGB 888 */
  250. 16,
  251. COLOR_ACTIVE,
  252. },
  253. [2] = {
  254. WVGA,
  255. 24, /* RGB 888 */
  256. 16,
  257. COLOR_ACTIVE,
  258. },
  259. };
  260. static const struct lcd_ctrl_config lcd_cfgs[] = {
  261. [0] = {
  262. &disp_panels[0],
  263. .ac_bias = 255,
  264. .ac_bias_intrpt = 0,
  265. .dma_burst_sz = 16,
  266. .bpp = 16,
  267. .fdd = 0x80,
  268. .tft_alt_mode = 0,
  269. .stn_565_mode = 0,
  270. .mono_8bit_mode = 0,
  271. .invert_line_clock = 1,
  272. .invert_frm_clock = 1,
  273. .sync_edge = 0,
  274. .sync_ctrl = 1,
  275. .raster_order = 0,
  276. },
  277. [1] = {
  278. &disp_panels[1],
  279. .ac_bias = 255,
  280. .ac_bias_intrpt = 0,
  281. .dma_burst_sz = 16,
  282. .bpp = 16,
  283. .fdd = 0x80,
  284. .tft_alt_mode = 0,
  285. .stn_565_mode = 0,
  286. .mono_8bit_mode = 0,
  287. .invert_line_clock = 1,
  288. .invert_frm_clock = 1,
  289. .sync_edge = 0,
  290. .sync_ctrl = 1,
  291. .raster_order = 0,
  292. },
  293. [2] = {
  294. &disp_panels[2],
  295. .ac_bias = 255,
  296. .ac_bias_intrpt = 0,
  297. .dma_burst_sz = 16,
  298. .bpp = 24,
  299. .fdd = 0x80,
  300. .tft_alt_mode = 0,
  301. .stn_565_mode = 0,
  302. .mono_8bit_mode = 0,
  303. .invert_line_clock = 1,
  304. .invert_frm_clock = 1,
  305. .sync_edge = 0,
  306. .sync_ctrl = 1,
  307. .raster_order = 0,
  308. },
  309. };
  310. /* no console on this board */
  311. int board_cfb_skip(void)
  312. {
  313. return 1;
  314. }
  315. #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
  316. #define PLL_GET_N(v) (v & 0x7f)
  317. static struct dpll_regs dpll_lcd_regs = {
  318. .cm_clkmode_dpll = CM_WKUP + 0x98,
  319. .cm_idlest_dpll = CM_WKUP + 0x48,
  320. .cm_clksel_dpll = CM_WKUP + 0x54,
  321. };
  322. static int get_clk(struct dpll_regs *dpll_regs)
  323. {
  324. unsigned int val;
  325. unsigned int m, n;
  326. int f = 0;
  327. val = readl(dpll_regs->cm_clksel_dpll);
  328. m = PLL_GET_M(val);
  329. n = PLL_GET_N(val);
  330. f = (m * V_OSCK) / n;
  331. return f;
  332. };
  333. int clk_get(int clk)
  334. {
  335. return get_clk(&dpll_lcd_regs);
  336. };
  337. static int conf_disp_pll(int m, int n)
  338. {
  339. struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  340. struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
  341. #if defined(DISPL_PLL_SPREAD_SPECTRUM)
  342. struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  343. #endif
  344. u32 *const clk_domains[] = {
  345. &cmper->lcdclkctrl,
  346. 0
  347. };
  348. u32 *const clk_modules_explicit_en[] = {
  349. &cmper->lcdclkctrl,
  350. &cmper->lcdcclkstctrl,
  351. &cmper->spi1clkctrl,
  352. 0
  353. };
  354. do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
  355. do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
  356. #if defined(DISPL_PLL_SPREAD_SPECTRUM)
  357. writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
  358. writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
  359. writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
  360. &cmwkup->clkmoddplldisp); /* 0x98 */
  361. #endif
  362. return 0;
  363. }
  364. static int set_gpio(int gpio, int state)
  365. {
  366. gpio_request(gpio, "temp");
  367. gpio_direction_output(gpio, state);
  368. gpio_set_value(gpio, state);
  369. gpio_free(gpio);
  370. return 0;
  371. }
  372. static int enable_lcd(void)
  373. {
  374. unsigned char buf[1];
  375. set_gpio(BOARD_LCD_RESET, 0);
  376. mdelay(1);
  377. set_gpio(BOARD_LCD_RESET, 1);
  378. mdelay(1);
  379. /* spi lcd init */
  380. kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
  381. /* backlight on */
  382. buf[0] = 0xf;
  383. i2c_write(0x24, 0x7, 1, buf, 1);
  384. buf[0] = 0x3f;
  385. i2c_write(0x24, 0x8, 1, buf, 1);
  386. return 0;
  387. }
  388. int arch_early_init_r(void)
  389. {
  390. enable_lcd();
  391. return 0;
  392. }
  393. static int board_video_init(void)
  394. {
  395. int i;
  396. int anzdisp = ARRAY_SIZE(lcd_panels);
  397. int display = 1;
  398. for (i = 0; i < anzdisp; i++) {
  399. if (strncmp((const char *)factory_dat.disp_name,
  400. lcd_panels[i].name,
  401. strlen((const char *)factory_dat.disp_name)) == 0) {
  402. printf("DISPLAY: %s\n", factory_dat.disp_name);
  403. break;
  404. }
  405. }
  406. if (i == anzdisp) {
  407. i = 1;
  408. printf("%s: %s not found, using default %s\n", __func__,
  409. factory_dat.disp_name, lcd_panels[i].name);
  410. }
  411. conf_disp_pll(24, 1);
  412. da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
  413. lcd_cfgs[display].bpp);
  414. return 0;
  415. }
  416. #endif /* ifdef CONFIG_VIDEO */
  417. #ifdef CONFIG_BOARD_LATE_INIT
  418. int board_late_init(void)
  419. {
  420. int ret;
  421. char tmp[2 * MAX_STRING_LENGTH + 2];
  422. omap_nand_switch_ecc(1, 8);
  423. if (factory_dat.asn[0] != 0)
  424. sprintf(tmp, "%s_%s", factory_dat.asn,
  425. factory_dat.comp_version);
  426. else
  427. strcpy(tmp, "QMX7.E38_4.0");
  428. ret = env_set("boardid", tmp);
  429. if (ret)
  430. printf("error setting board id\n");
  431. return 0;
  432. }
  433. #endif
  434. #include "../common/board.c"