mx6quq7-2g.cfg 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2013 Seco USA Inc
  4. *
  5. * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
  6. * and create imximage boot image
  7. *
  8. * The syntax is taken as close as possible with the kwbimage
  9. */
  10. /* image version */
  11. IMAGE_VERSION 2
  12. /*
  13. * Boot Device : one of
  14. * spi, sd (the board has no nand neither onenand)
  15. */
  16. BOOT_FROM sd
  17. #define __ASSEMBLY__
  18. #include <config.h>
  19. #include "asm/arch/mx6-ddr.h"
  20. #include "asm/arch/iomux.h"
  21. #include "asm/arch/crm_regs.h"
  22. /* DDR IO TYPE */
  23. DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
  24. DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
  25. /* DATA STROBE */
  26. DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
  27. DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
  28. DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
  29. DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
  30. DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
  31. DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
  32. DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
  33. DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
  34. DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028
  35. /* DATA */
  36. DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
  37. DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
  38. DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
  39. DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
  40. DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
  41. DATA 4, MX6_IOM_GRP_B4DS, 0x00000028
  42. DATA 4, MX6_IOM_GRP_B5DS, 0x00000028
  43. DATA 4, MX6_IOM_GRP_B6DS, 0x00000028
  44. DATA 4, MX6_IOM_GRP_B7DS, 0x00000028
  45. DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
  46. DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
  47. DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
  48. DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
  49. DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028
  50. DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028
  51. DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028
  52. DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028
  53. /* ADDRESS */
  54. DATA 4, MX6_IOM_GRP_ADDDS, 0x00000028
  55. DATA 4, MX6_IOM_DRAM_CAS, 0x00000028
  56. DATA 4, MX6_IOM_DRAM_RAS, 0x00000028
  57. /* CONTROL */
  58. DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
  59. DATA 4, MX6_IOM_DRAM_RESET, 0x00000028
  60. DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
  61. DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000028
  62. DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000028
  63. /* CLOCK */
  64. DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
  65. DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
  66. /*
  67. * DDR3 SETTINGS
  68. * Read Data Bit Delay
  69. */
  70. DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
  71. DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
  72. DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
  73. DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
  74. DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
  75. DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
  76. DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
  77. DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
  78. /* Write Leveling */
  79. DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
  80. DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
  81. DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F0001
  82. DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
  83. /* DQS gating, read delay, write delay calibration values */
  84. DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x431A0326
  85. DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0323031B
  86. DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x433F0340
  87. DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0345031C
  88. /* Read calibration */
  89. DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40343137
  90. DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x40372F45
  91. /* write calibration */
  92. DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x32414741
  93. DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4731473C
  94. /* Complete calibration by forced measurement: */
  95. DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
  96. DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
  97. /*
  98. * MMDC init:
  99. * in DDR3, 64-bit mode, only MMDC0 is init
  100. */
  101. DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
  102. DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
  103. DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7955
  104. DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
  105. DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
  106. DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
  107. DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
  108. DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
  109. DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
  110. /* CS0_END = 2304MB in step da 256Mb -> [(2304*8/256) - 1] */
  111. DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
  112. /* SDE_1=0; ROW=3; BL=1; DSIZ=2 -> 64 bit */
  113. DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
  114. /* Initialize DDR3 on CS_0 and CS_1 */
  115. DATA 4, MX6_MMDC_P0_MDSCR, 0x02088032
  116. DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
  117. DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
  118. /* P0 01c */
  119. /* write 0x0940 to MR0 bank_0 (Burst Type=1 (Interlived)) */
  120. DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
  121. /*ZQ - Calibrationi */
  122. DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
  123. DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
  124. DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
  125. DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
  126. DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
  127. DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
  128. DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
  129. DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
  130. /* set the default clock gate to save power */
  131. DATA 4, CCM_CCGR0, 0x00C03F3F
  132. DATA 4, CCM_CCGR1, 0x0030FC03
  133. DATA 4, CCM_CCGR2, 0x0FFFC000
  134. DATA 4, CCM_CCGR3, 0x3FF00000
  135. DATA 4, CCM_CCGR4, 0x00FFF300
  136. DATA 4, CCM_CCGR5, 0x0F0000C3
  137. DATA 4, CCM_CCGR6, 0x000003FF
  138. /* enable AXI cache for VDOA/VPU/IPU */
  139. DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
  140. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  141. DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
  142. DATA 4, MX6_IOMUXC_GPR7, 0x007F007F