sbc8349.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sbc8349.c -- WindRiver SBC8349 board support.
  4. * Copyright (c) 2006-2007 Wind River Systems, Inc.
  5. *
  6. * Paul Gortmaker <paul.gortmaker@windriver.com>
  7. * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
  8. */
  9. #include <common.h>
  10. #include <fdt_support.h>
  11. #include <init.h>
  12. #include <ioports.h>
  13. #include <mpc83xx.h>
  14. #include <asm/bitops.h>
  15. #include <asm/mpc8349_pci.h>
  16. #include <i2c.h>
  17. #include <spd_sdram.h>
  18. #include <miiphy.h>
  19. #if defined(CONFIG_OF_LIBFDT)
  20. #include <linux/libfdt.h>
  21. #endif
  22. #include <linux/delay.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int fixed_sdram(void);
  25. void sdram_init(void);
  26. #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
  27. void ddr_enable_ecc(unsigned int dram_size);
  28. #endif
  29. #ifdef CONFIG_BOARD_EARLY_INIT_F
  30. int board_early_init_f (void)
  31. {
  32. return 0;
  33. }
  34. #endif
  35. #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
  36. int dram_init(void)
  37. {
  38. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  39. u32 msize = 0;
  40. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  41. return -1;
  42. /* DDR SDRAM - Main SODIMM */
  43. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
  44. #if defined(CONFIG_SPD_EEPROM)
  45. msize = spd_sdram();
  46. #else
  47. msize = fixed_sdram();
  48. #endif
  49. /*
  50. * Initialize SDRAM if it is on local bus.
  51. */
  52. sdram_init();
  53. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  54. /*
  55. * Initialize and enable DDR ECC.
  56. */
  57. ddr_enable_ecc(msize * 1024 * 1024);
  58. #endif
  59. /* set total bus SDRAM size(bytes) -- DDR */
  60. gd->ram_size = msize * 1024 * 1024;
  61. return 0;
  62. }
  63. #if !defined(CONFIG_SPD_EEPROM)
  64. /*************************************************************************
  65. * fixed sdram init -- doesn't use serial presence detect.
  66. ************************************************************************/
  67. int fixed_sdram(void)
  68. {
  69. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  70. u32 msize = CONFIG_SYS_DDR_SIZE;
  71. u32 ddr_size = msize << 20; /* DDR size in bytes */
  72. u32 ddr_size_log2 = __ilog2(msize);
  73. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  74. im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  75. #if (CONFIG_SYS_DDR_SIZE != 256)
  76. #warning Currently any ddr size other than 256 is not supported
  77. #endif
  78. #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  79. #warning Chip select bounds is only configurable in 16MB increments
  80. #endif
  81. im->ddr.csbnds[2].csbnds =
  82. ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  83. (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
  84. CSBNDS_EA_SHIFT) & CSBNDS_EA);
  85. im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
  86. /* currently we use only one CS, so disable the other banks */
  87. im->ddr.cs_config[0] = 0;
  88. im->ddr.cs_config[1] = 0;
  89. im->ddr.cs_config[3] = 0;
  90. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  91. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  92. im->ddr.sdram_cfg =
  93. SDRAM_CFG_SREN
  94. #if defined(CONFIG_DDR_2T_TIMING)
  95. | SDRAM_CFG_2T_EN
  96. #endif
  97. | SDRAM_CFG_SDRAM_TYPE_DDR1;
  98. #if defined (CONFIG_DDR_32BIT)
  99. /* for 32-bit mode burst length is 8 */
  100. im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
  101. #endif
  102. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  103. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  104. udelay(200);
  105. /* enable DDR controller */
  106. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  107. return msize;
  108. }
  109. #endif/*!CONFIG_SYS_SPD_EEPROM*/
  110. int checkboard (void)
  111. {
  112. puts("Board: Wind River SBC834x\n");
  113. return 0;
  114. }
  115. /*
  116. * if board is fitted with SDRAM
  117. */
  118. #if defined(CONFIG_SYS_BR2_PRELIM) \
  119. && defined(CONFIG_SYS_OR2_PRELIM) \
  120. && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
  121. && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
  122. /*
  123. * Initialize SDRAM memory on the Local Bus.
  124. */
  125. void sdram_init(void)
  126. {
  127. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  128. volatile fsl_lbc_t *lbc = &immap->im_lbc;
  129. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  130. const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
  131. LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
  132. LSDMR_WRC3 | LSDMR_CL3;
  133. puts("\n SDRAM on Local Bus: ");
  134. print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  135. /*
  136. * Setup SDRAM Base and Option Registers, already done in cpu_init.c
  137. */
  138. /* setup mtrpt, lsrt and lbcr for LB bus */
  139. lbc->lbcr = 0x00000000;
  140. /* LB refresh timer prescal, 266MHz/32 */
  141. lbc->mrtpr = 0x20000000;
  142. /* LB sdram refresh timer, about 6us */
  143. lbc->lsrt = 0x32000000;
  144. asm("sync");
  145. /*
  146. * Configure the SDRAM controller Machine Mode Register.
  147. */
  148. /* 0x40636733; normal operation */
  149. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  150. /* 0x68636733; precharge all the banks */
  151. lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
  152. asm("sync");
  153. *sdram_addr = 0xff;
  154. udelay(100);
  155. /* 0x48636733; auto refresh */
  156. lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
  157. asm("sync");
  158. /*1 times*/
  159. *sdram_addr = 0xff;
  160. udelay(100);
  161. /*2 times*/
  162. *sdram_addr = 0xff;
  163. udelay(100);
  164. /*3 times*/
  165. *sdram_addr = 0xff;
  166. udelay(100);
  167. /*4 times*/
  168. *sdram_addr = 0xff;
  169. udelay(100);
  170. /*5 times*/
  171. *sdram_addr = 0xff;
  172. udelay(100);
  173. /*6 times*/
  174. *sdram_addr = 0xff;
  175. udelay(100);
  176. /*7 times*/
  177. *sdram_addr = 0xff;
  178. udelay(100);
  179. /*8 times*/
  180. *sdram_addr = 0xff;
  181. udelay(100);
  182. /* 0x58636733; mode register write operation */
  183. lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
  184. asm("sync");
  185. *sdram_addr = 0xff;
  186. udelay(100);
  187. /* 0x40636733; normal operation */
  188. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  189. asm("sync");
  190. *sdram_addr = 0xff;
  191. udelay(100);
  192. }
  193. #else
  194. void sdram_init(void)
  195. {
  196. puts(" SDRAM on Local Bus: Disabled in config\n");
  197. }
  198. #endif
  199. #if defined(CONFIG_OF_BOARD_SETUP)
  200. int ft_board_setup(void *blob, struct bd_info *bd)
  201. {
  202. ft_cpu_setup(blob, bd);
  203. #ifdef CONFIG_PCI
  204. ft_pci_setup(blob, bd);
  205. #endif
  206. return 0;
  207. }
  208. #endif