stout_spl.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/stout/stout_spl.c
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <malloc.h>
  11. #include <dm/platform_data/serial_sh.h>
  12. #include <asm/processor.h>
  13. #include <asm/mach-types.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. #include <linux/errno.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/gpio.h>
  19. #include <asm/arch/rmobile.h>
  20. #include <asm/arch/rcar-mstp.h>
  21. #include <spl.h>
  22. #define TMU0_MSTP125 BIT(25)
  23. #define SCIFA0_MSTP204 BIT(4)
  24. #define QSPI_MSTP917 BIT(17)
  25. #define SD2CKCR 0xE615026C
  26. #define SD_97500KHZ 0x7
  27. struct reg_config {
  28. u16 off;
  29. u32 val;
  30. };
  31. static void dbsc_wait(u16 reg)
  32. {
  33. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  34. static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
  35. while (!(readl(dbsc3_0_base + reg) & BIT(0)))
  36. ;
  37. while (!(readl(dbsc3_1_base + reg) & BIT(0)))
  38. ;
  39. }
  40. static void spl_init_sys(void)
  41. {
  42. u32 r0 = 0;
  43. writel(0xa5a5a500, 0xe6020004);
  44. writel(0xa5a5a500, 0xe6030004);
  45. asm volatile(
  46. /* ICIALLU - Invalidate I$ to PoU */
  47. "mcr 15, 0, %0, cr7, cr5, 0 \n"
  48. /* BPIALL - Invalidate branch predictors */
  49. "mcr 15, 0, %0, cr7, cr5, 6 \n"
  50. /* Set SCTLR[IZ] */
  51. "mrc 15, 0, %0, cr1, cr0, 0 \n"
  52. "orr %0, #0x1800 \n"
  53. "mcr 15, 0, %0, cr1, cr0, 0 \n"
  54. "isb sy \n"
  55. :"=r"(r0));
  56. }
  57. static void spl_init_pfc(void)
  58. {
  59. static const struct reg_config pfc_with_unlock[] = {
  60. { 0x0090, 0x00140300 },
  61. { 0x0094, 0x09500000 },
  62. { 0x0098, 0xc0000084 },
  63. { 0x0020, 0x01a33492 },
  64. { 0x0024, 0x10000000 },
  65. { 0x0028, 0x08449252 },
  66. { 0x002c, 0x2925b322 },
  67. { 0x0030, 0x0c311249 },
  68. { 0x0034, 0x10124000 },
  69. { 0x0038, 0x00001295 },
  70. { 0x003c, 0x50890000 },
  71. { 0x0040, 0x0eaa56aa },
  72. { 0x0044, 0x55550000 },
  73. { 0x0048, 0x00000005 },
  74. { 0x004c, 0x54800000 },
  75. { 0x0050, 0x3736db55 },
  76. { 0x0054, 0x29148da3 },
  77. { 0x0058, 0x48c446e1 },
  78. { 0x005c, 0x2a3a54dc },
  79. { 0x0160, 0x00000023 },
  80. { 0x0004, 0xfca0ffff },
  81. { 0x0008, 0x3fbffbf0 },
  82. { 0x000c, 0x3ffdffff },
  83. { 0x0010, 0x00ffffff },
  84. { 0x0014, 0xfc3ffff3 },
  85. { 0x0018, 0xe4fdfff7 },
  86. };
  87. static const struct reg_config pfc_without_unlock[] = {
  88. { 0x0104, 0xffffbfff },
  89. { 0x0108, 0xb1ffffe1 },
  90. { 0x010c, 0xffffffff },
  91. { 0x0110, 0xffffffff },
  92. { 0x0114, 0xe047beab },
  93. { 0x0118, 0x00000203 },
  94. };
  95. static const u32 pfc_base = 0xe6060000;
  96. unsigned int i;
  97. for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
  98. writel(~pfc_with_unlock[i].val, pfc_base);
  99. writel(pfc_with_unlock[i].val,
  100. pfc_base | pfc_with_unlock[i].off);
  101. }
  102. for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
  103. writel(pfc_without_unlock[i].val,
  104. pfc_base | pfc_without_unlock[i].off);
  105. }
  106. static void spl_init_gpio(void)
  107. {
  108. static const u16 gpio_offs[] = {
  109. 0x1000, 0x3000, 0x4000, 0x5000
  110. };
  111. static const struct reg_config gpio_set[] = {
  112. { 0x4000, 0x00c00000 },
  113. { 0x5000, 0x63020000 },
  114. };
  115. static const struct reg_config gpio_clr[] = {
  116. { 0x1000, 0x00000000 },
  117. { 0x3000, 0x00000000 },
  118. { 0x4000, 0x00c00000 },
  119. { 0x5000, 0xe3020000 },
  120. };
  121. static const u32 gpio_base = 0xe6050000;
  122. unsigned int i;
  123. for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
  124. writel(0, gpio_base | 0x20 | gpio_offs[i]);
  125. for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
  126. writel(0, gpio_base | 0x00 | gpio_offs[i]);
  127. for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
  128. writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
  129. for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
  130. writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
  131. }
  132. static void spl_init_lbsc(void)
  133. {
  134. static const struct reg_config lbsc_config[] = {
  135. { 0x00, 0x00000020 },
  136. { 0x08, 0x00002020 },
  137. { 0x30, 0x02150326 },
  138. { 0x38, 0x077f077f },
  139. };
  140. static const u16 lbsc_offs[] = {
  141. 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
  142. };
  143. static const u32 lbsc_base = 0xfec00200;
  144. unsigned int i;
  145. for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
  146. writel(lbsc_config[i].val,
  147. lbsc_base | lbsc_config[i].off);
  148. writel(lbsc_config[i].val,
  149. lbsc_base | (lbsc_config[i].off + 4));
  150. }
  151. for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
  152. writel(0, lbsc_base | lbsc_offs[i]);
  153. }
  154. static void spl_init_dbsc(void)
  155. {
  156. static const struct reg_config dbsc_config1[] = {
  157. { 0x0280, 0x0000a55a },
  158. { 0x0018, 0x21000000 },
  159. { 0x0018, 0x11000000 },
  160. { 0x0018, 0x10000000 },
  161. { 0x0290, 0x00000001 },
  162. { 0x02a0, 0x80000000 },
  163. { 0x0290, 0x00000004 },
  164. };
  165. static const struct reg_config dbsc_config2[] = {
  166. { 0x0290, 0x00000006 },
  167. { 0x02a0, 0x0001c000 },
  168. };
  169. static const struct reg_config dbsc_config3r0d0[] = {
  170. { 0x0290, 0x0000000f },
  171. { 0x02a0, 0x00181885 },
  172. { 0x0290, 0x00000070 },
  173. { 0x02a0, 0x7c000887 },
  174. { 0x0290, 0x00000080 },
  175. { 0x02a0, 0x7c000887 },
  176. { 0x0290, 0x00000090 },
  177. { 0x02a0, 0x7c000887 },
  178. { 0x0290, 0x000000a0 },
  179. { 0x02a0, 0x7c000887 },
  180. { 0x0290, 0x000000b0 },
  181. { 0x02a0, 0x7c000880 },
  182. { 0x0290, 0x000000c0 },
  183. { 0x02a0, 0x7c000880 },
  184. { 0x0290, 0x000000d0 },
  185. { 0x02a0, 0x7c000880 },
  186. { 0x0290, 0x000000e0 },
  187. { 0x02a0, 0x7c000880 },
  188. };
  189. static const struct reg_config dbsc_config3r0d1[] = {
  190. { 0x0290, 0x0000000f },
  191. { 0x02a0, 0x00181885 },
  192. { 0x0290, 0x00000070 },
  193. { 0x02a0, 0x7c000887 },
  194. { 0x0290, 0x00000080 },
  195. { 0x02a0, 0x7c000887 },
  196. { 0x0290, 0x00000090 },
  197. { 0x02a0, 0x7c000887 },
  198. { 0x0290, 0x000000a0 },
  199. { 0x02a0, 0x7c000887 },
  200. };
  201. static const struct reg_config dbsc_config3r2[] = {
  202. { 0x0290, 0x0000000f },
  203. { 0x02a0, 0x00181224 },
  204. };
  205. static const struct reg_config dbsc_config4[] = {
  206. { 0x0290, 0x00000010 },
  207. { 0x02a0, 0xf004649b },
  208. { 0x0290, 0x00000061 },
  209. { 0x02a0, 0x0000006d },
  210. { 0x0290, 0x00000001 },
  211. { 0x02a0, 0x00000073 },
  212. { 0x0020, 0x00000007 },
  213. { 0x0024, 0x0f030a02 },
  214. { 0x0030, 0x00000001 },
  215. { 0x00b0, 0x00000000 },
  216. { 0x0040, 0x0000000b },
  217. { 0x0044, 0x00000008 },
  218. { 0x0048, 0x00000000 },
  219. { 0x0050, 0x0000000b },
  220. { 0x0054, 0x000c000b },
  221. { 0x0058, 0x00000027 },
  222. { 0x005c, 0x0000001c },
  223. { 0x0060, 0x00000006 },
  224. { 0x0064, 0x00000020 },
  225. { 0x0068, 0x00000008 },
  226. { 0x006c, 0x0000000c },
  227. { 0x0070, 0x00000009 },
  228. { 0x0074, 0x00000012 },
  229. { 0x0078, 0x000000d0 },
  230. { 0x007c, 0x00140005 },
  231. { 0x0080, 0x00050004 },
  232. { 0x0084, 0x70233005 },
  233. { 0x0088, 0x000c0000 },
  234. { 0x008c, 0x00000200 },
  235. { 0x0090, 0x00000040 },
  236. { 0x0100, 0x00000001 },
  237. { 0x00c0, 0x00020001 },
  238. { 0x00c8, 0x20042004 },
  239. { 0x0380, 0x00020002 },
  240. { 0x0390, 0x0000001f },
  241. };
  242. static const struct reg_config dbsc_config5[] = {
  243. { 0x0244, 0x00000011 },
  244. { 0x0290, 0x00000003 },
  245. { 0x02a0, 0x0300c4e1 },
  246. { 0x0290, 0x00000023 },
  247. { 0x02a0, 0x00fcdb60 },
  248. { 0x0290, 0x00000011 },
  249. { 0x02a0, 0x1000040b },
  250. { 0x0290, 0x00000012 },
  251. { 0x02a0, 0x9d9cbb66 },
  252. { 0x0290, 0x00000013 },
  253. { 0x02a0, 0x1a868400 },
  254. { 0x0290, 0x00000014 },
  255. { 0x02a0, 0x300214d8 },
  256. { 0x0290, 0x00000015 },
  257. { 0x02a0, 0x00000d70 },
  258. { 0x0290, 0x00000016 },
  259. { 0x02a0, 0x00000006 },
  260. { 0x0290, 0x00000017 },
  261. { 0x02a0, 0x00000018 },
  262. { 0x0290, 0x0000001a },
  263. { 0x02a0, 0x910035c7 },
  264. { 0x0290, 0x00000004 },
  265. };
  266. static const struct reg_config dbsc_config6[] = {
  267. { 0x0290, 0x00000001 },
  268. { 0x02a0, 0x00000181 },
  269. { 0x0018, 0x11000000 },
  270. { 0x0290, 0x00000004 },
  271. };
  272. static const struct reg_config dbsc_config7[] = {
  273. { 0x0290, 0x00000001 },
  274. { 0x02a0, 0x0000fe01 },
  275. { 0x0304, 0x00000000 },
  276. { 0x00f4, 0x01004c20 },
  277. { 0x00f8, 0x014000aa },
  278. { 0x00e0, 0x00000140 },
  279. { 0x00e4, 0x00081860 },
  280. { 0x00e8, 0x00010000 },
  281. { 0x0290, 0x00000004 },
  282. };
  283. static const struct reg_config dbsc_config8[] = {
  284. { 0x0014, 0x00000001 },
  285. { 0x0010, 0x00000001 },
  286. { 0x0280, 0x00000000 },
  287. };
  288. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  289. static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
  290. static const u32 prr_base = 0xff000044;
  291. const u16 prr_rev = readl(prr_base) & 0x7fff;
  292. unsigned int i;
  293. for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
  294. writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
  295. writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
  296. }
  297. dbsc_wait(0x2a0);
  298. for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
  299. writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
  300. writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
  301. }
  302. if (prr_rev == 0x4500) {
  303. for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
  304. writel(dbsc_config3r0d0[i].val,
  305. dbsc3_0_base | dbsc_config3r0d0[i].off);
  306. }
  307. for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
  308. writel(dbsc_config3r0d1[i].val,
  309. dbsc3_1_base | dbsc_config3r0d1[i].off);
  310. }
  311. } else if (prr_rev != 0x4510) {
  312. for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
  313. writel(dbsc_config3r2[i].val,
  314. dbsc3_0_base | dbsc_config3r2[i].off);
  315. writel(dbsc_config3r2[i].val,
  316. dbsc3_1_base | dbsc_config3r2[i].off);
  317. }
  318. }
  319. for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
  320. writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
  321. writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
  322. }
  323. dbsc_wait(0x240);
  324. for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
  325. writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
  326. writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
  327. }
  328. dbsc_wait(0x2a0);
  329. for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
  330. writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
  331. writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
  332. }
  333. dbsc_wait(0x2a0);
  334. for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
  335. writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
  336. writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
  337. }
  338. dbsc_wait(0x2a0);
  339. for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
  340. writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
  341. writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
  342. }
  343. }
  344. static void spl_init_qspi(void)
  345. {
  346. mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
  347. static const u32 qspi_base = 0xe6b10000;
  348. writeb(0x08, qspi_base + 0x00);
  349. writeb(0x00, qspi_base + 0x01);
  350. writeb(0x06, qspi_base + 0x02);
  351. writeb(0x01, qspi_base + 0x0a);
  352. writeb(0x00, qspi_base + 0x0b);
  353. writeb(0x00, qspi_base + 0x0c);
  354. writeb(0x00, qspi_base + 0x0d);
  355. writeb(0x00, qspi_base + 0x0e);
  356. writew(0xe080, qspi_base + 0x10);
  357. writeb(0xc0, qspi_base + 0x18);
  358. writeb(0x00, qspi_base + 0x18);
  359. writeb(0x00, qspi_base + 0x08);
  360. writeb(0x48, qspi_base + 0x00);
  361. }
  362. void board_init_f(ulong dummy)
  363. {
  364. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  365. mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
  366. /*
  367. * SD0 clock is set to 97.5MHz by default.
  368. * Set SD2 to the 97.5MHz as well.
  369. */
  370. writel(SD_97500KHZ, SD2CKCR);
  371. spl_init_sys();
  372. spl_init_pfc();
  373. spl_init_gpio();
  374. spl_init_lbsc();
  375. spl_init_dbsc();
  376. spl_init_qspi();
  377. }
  378. void spl_board_init(void)
  379. {
  380. /* UART clocks enabled and gd valid - init serial console */
  381. preloader_console_init();
  382. }
  383. void board_boot_order(u32 *spl_boot_list)
  384. {
  385. const u32 jtag_magic = 0x1337c0de;
  386. const u32 load_magic = 0xb33fc0de;
  387. /*
  388. * If JTAG probe sets special word at 0xe6300020, then it must
  389. * put U-Boot into RAM and SPL will start it from RAM.
  390. */
  391. if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
  392. printf("JTAG boot detected!\n");
  393. while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
  394. ;
  395. spl_boot_list[0] = BOOT_DEVICE_RAM;
  396. spl_boot_list[1] = BOOT_DEVICE_NONE;
  397. return;
  398. }
  399. /* Boot from SPI NOR with YMODEM UART fallback. */
  400. spl_boot_list[0] = BOOT_DEVICE_SPI;
  401. spl_boot_list[1] = BOOT_DEVICE_UART;
  402. spl_boot_list[2] = BOOT_DEVICE_NONE;
  403. }
  404. void reset_cpu(ulong addr)
  405. {
  406. }