spi-boot.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Renesas Solutions Corp.
  4. */
  5. #include <common.h>
  6. #define CONFIG_SPI_ADDR 0x00000000
  7. #define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000)
  8. #define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE)
  9. #define SPIWDMADR 0xFE001018
  10. #define SPIWDMCNTR 0xFE001020
  11. #define SPIDMCOR 0xFE001028
  12. #define SPIDMINTSR 0xFE001188
  13. #define SPIDMINTMR 0xFE001190
  14. #define SPIDMINTSR_DMEND 0x00000004
  15. #define TBR 0xFE002000
  16. #define RBR 0xFE002000
  17. #define CR1 0xFE002008
  18. #define CR2 0xFE002010
  19. #define CR3 0xFE002018
  20. #define CR4 0xFE002020
  21. #define CR7 0xFE002038
  22. #define CR8 0xFE002040
  23. /* CR1 */
  24. #define SPI_TBE 0x80
  25. #define SPI_TBF 0x40
  26. #define SPI_RBE 0x20
  27. #define SPI_RBF 0x10
  28. #define SPI_PFONRD 0x08
  29. #define SPI_SSDB 0x04
  30. #define SPI_SSD 0x02
  31. #define SPI_SSA 0x01
  32. /* CR2 */
  33. #define SPI_RSTF 0x80
  34. #define SPI_LOOPBK 0x40
  35. #define SPI_CPOL 0x20
  36. #define SPI_CPHA 0x10
  37. #define SPI_L1M0 0x08
  38. /* CR4 */
  39. #define SPI_TBEI 0x80
  40. #define SPI_TBFI 0x40
  41. #define SPI_RBEI 0x20
  42. #define SPI_RBFI 0x10
  43. #define SPI_SpiS0 0x02
  44. #define SPI_SSS 0x01
  45. /* CR7 */
  46. #define CR7_IDX_OR12 0x12
  47. #define OR12_ADDR32 0x00000001
  48. #define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
  49. #define spi_read(addr) (*(volatile unsigned long *)(addr))
  50. /* M25P80 */
  51. #define M25_READ 0x03
  52. #define M25_READ_4BYTE 0x13
  53. extern void bss_start(void);
  54. #define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
  55. static void __uses_spiboot2 spi_reset(void)
  56. {
  57. int timeout = 0x00100000;
  58. /* Make sure the last transaction is finalized */
  59. spi_write(0x00, CR3);
  60. spi_write(0x02, CR1);
  61. while (!(spi_read(CR4) & SPI_SpiS0)) {
  62. if (timeout-- < 0)
  63. break;
  64. }
  65. spi_write(0x00, CR1);
  66. spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
  67. spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
  68. spi_write(0, SPIDMCOR);
  69. }
  70. static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
  71. unsigned long len)
  72. {
  73. spi_write(CR7_IDX_OR12, CR7);
  74. if (spi_read(CR8) & OR12_ADDR32) {
  75. /* 4-bytes address mode */
  76. spi_write(M25_READ_4BYTE, TBR);
  77. spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */
  78. } else {
  79. /* 3-bytes address mode */
  80. spi_write(M25_READ, TBR);
  81. }
  82. spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */
  83. spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */
  84. spi_write(addr & 0xFF, TBR); /* ADDR7-0 */
  85. spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
  86. spi_write((unsigned long)buf, SPIWDMADR);
  87. spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
  88. spi_write(1, SPIDMCOR);
  89. spi_write(0xff, CR3);
  90. spi_write(spi_read(CR1) | SPI_SSDB, CR1);
  91. spi_write(spi_read(CR1) | SPI_SSA, CR1);
  92. while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
  93. ;
  94. /* Nagate SP0-SS0 */
  95. spi_write(0, CR1);
  96. }
  97. void __uses_spiboot2 spiboot_main(void)
  98. {
  99. /*
  100. * This code rounds len up for SPIWDMCNTR. We should set it to 0 in
  101. * lower 5-bits.
  102. */
  103. void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
  104. volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0;
  105. spi_reset();
  106. spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len);
  107. _start();
  108. }