sh7753evb.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Renesas Solutions Corp.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <flash.h>
  9. #include <init.h>
  10. #include <malloc.h>
  11. #include <net.h>
  12. #include <asm/processor.h>
  13. #include <asm/io.h>
  14. #include <asm/mmc.h>
  15. #include <spi.h>
  16. #include <spi_flash.h>
  17. #include <linux/delay.h>
  18. int checkboard(void)
  19. {
  20. puts("BOARD: SH7753 EVB\n");
  21. return 0;
  22. }
  23. static void init_gpio(void)
  24. {
  25. struct gpio_regs *gpio = GPIO_BASE;
  26. struct sermux_regs *sermux = SERMUX_BASE;
  27. /* GPIO */
  28. writew(0x0000, &gpio->pacr); /* GETHER */
  29. writew(0x0001, &gpio->pbcr); /* INTC */
  30. writew(0x0000, &gpio->pccr); /* PWMU, INTC */
  31. writew(0x0000, &gpio->pdcr); /* SPI0 */
  32. writew(0xeaff, &gpio->pecr); /* GPIO */
  33. writew(0x0000, &gpio->pfcr); /* WDT */
  34. writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
  35. writew(0x0000, &gpio->phcr); /* SPI1 */
  36. writew(0x0000, &gpio->picr); /* SDHI */
  37. writew(0x0000, &gpio->pjcr); /* SCIF4 */
  38. writew(0x0003, &gpio->pkcr); /* SerMux */
  39. writew(0x0000, &gpio->plcr); /* SerMux */
  40. writew(0x0000, &gpio->pmcr); /* RIIC */
  41. writew(0x0000, &gpio->pncr); /* USB, SGPIO */
  42. writew(0x0000, &gpio->pocr); /* SGPIO */
  43. writew(0xd555, &gpio->pqcr); /* GPIO */
  44. writew(0x0000, &gpio->prcr); /* RIIC */
  45. writew(0x0000, &gpio->pscr); /* RIIC */
  46. writew(0x0000, &gpio->ptcr); /* STATUS */
  47. writeb(0x00, &gpio->pudr);
  48. writew(0x5555, &gpio->pucr); /* Debug LED */
  49. writew(0x0000, &gpio->pvcr); /* RSPI */
  50. writew(0x0000, &gpio->pwcr); /* EVC */
  51. writew(0x0000, &gpio->pxcr); /* LBSC */
  52. writew(0x0000, &gpio->pycr); /* LBSC */
  53. writew(0x0000, &gpio->pzcr); /* eMMC */
  54. writew(0xfe00, &gpio->psel0);
  55. writew(0x0000, &gpio->psel1);
  56. writew(0x3000, &gpio->psel2);
  57. writew(0xff00, &gpio->psel3);
  58. writew(0x771f, &gpio->psel4);
  59. writew(0x0ffc, &gpio->psel5);
  60. writew(0x00ff, &gpio->psel6);
  61. writew(0xfc00, &gpio->psel7);
  62. writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
  63. }
  64. static void init_usb_phy(void)
  65. {
  66. struct usb_common_regs *common0 = USB0_COMMON_BASE;
  67. struct usb_common_regs *common1 = USB1_COMMON_BASE;
  68. struct usb0_phy_regs *phy = USB0_PHY_BASE;
  69. struct usb1_port_regs *port = USB1_PORT_BASE;
  70. struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  71. writew(0x0100, &phy->reset); /* set reset */
  72. /* port0 = USB0, port1 = USB1 */
  73. writew(0x0002, &phy->portsel);
  74. writel(0x0001, &port->port1sel); /* port1 = Host */
  75. writew(0x0111, &phy->reset); /* clear reset */
  76. writew(0x4000, &common0->suspmode);
  77. writew(0x4000, &common1->suspmode);
  78. #if defined(__LITTLE_ENDIAN)
  79. writel(0x00000000, &align->ehcidatac);
  80. writel(0x00000000, &align->ohcidatac);
  81. #endif
  82. }
  83. static void init_gether_mdio(void)
  84. {
  85. struct gpio_regs *gpio = GPIO_BASE;
  86. writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
  87. writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
  88. }
  89. static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  90. {
  91. struct ether_mac_regs *ether;
  92. unsigned char mac[6];
  93. unsigned long val;
  94. string_to_enetaddr(mac_string, mac);
  95. if (!channel)
  96. ether = GETHER0_MAC_BASE;
  97. else
  98. ether = GETHER1_MAC_BASE;
  99. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  100. writel(val, &ether->mahr);
  101. val = (mac[4] << 8) | mac[5];
  102. writel(val, &ether->malr);
  103. }
  104. #if defined(CONFIG_SH_32BIT)
  105. /*****************************************************************
  106. * This PMB must be set on this timing. The lowlevel_init is run on
  107. * Area 0(phys 0x00000000), so we have to map it.
  108. *
  109. * The new PMB table is following:
  110. * ent virt phys v sz c wt
  111. * 0 0xa0000000 0x40000000 1 128M 0 1
  112. * 1 0xa8000000 0x48000000 1 128M 0 1
  113. * 2 0xb0000000 0x50000000 1 128M 0 1
  114. * 3 0xb8000000 0x58000000 1 128M 0 1
  115. * 4 0x80000000 0x40000000 1 128M 1 1
  116. * 5 0x88000000 0x48000000 1 128M 1 1
  117. * 6 0x90000000 0x50000000 1 128M 1 1
  118. * 7 0x98000000 0x58000000 1 128M 1 1
  119. */
  120. static void set_pmb_on_board_init(void)
  121. {
  122. struct mmu_regs *mmu = MMU_BASE;
  123. /* clear ITLB */
  124. writel(0x00000004, &mmu->mmucr);
  125. /* delete PMB for SPIBOOT */
  126. writel(0, PMB_ADDR_BASE(0));
  127. writel(0, PMB_DATA_BASE(0));
  128. /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  129. /* ppn ub v s1 s0 c wt */
  130. writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
  131. writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
  132. writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
  133. writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
  134. writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
  135. writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
  136. writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
  137. writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
  138. writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
  139. writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
  140. writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
  141. writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
  142. }
  143. #endif
  144. int board_init(void)
  145. {
  146. struct gether_control_regs *gether = GETHER_CONTROL_BASE;
  147. init_gpio();
  148. #if defined(CONFIG_SH_32BIT)
  149. set_pmb_on_board_init();
  150. #endif
  151. /* Sets TXnDLY to B'010 */
  152. writel(0x00000202, &gether->gbecont);
  153. init_usb_phy();
  154. init_gether_mdio();
  155. return 0;
  156. }
  157. int board_mmc_init(struct bd_info *bis)
  158. {
  159. struct gpio_regs *gpio = GPIO_BASE;
  160. writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
  161. writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
  162. udelay(1);
  163. writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
  164. udelay(200);
  165. return mmcif_mmc_init();
  166. }
  167. static int get_sh_eth_mac_raw(unsigned char *buf, int size)
  168. {
  169. #ifdef CONFIG_DEPRECATED
  170. struct spi_flash *spi;
  171. int ret;
  172. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  173. if (spi == NULL) {
  174. printf("%s: spi_flash probe failed.\n", __func__);
  175. return 1;
  176. }
  177. ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
  178. if (ret) {
  179. printf("%s: spi_flash read failed.\n", __func__);
  180. spi_flash_free(spi);
  181. return 1;
  182. }
  183. spi_flash_free(spi);
  184. #endif
  185. return 0;
  186. }
  187. static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
  188. {
  189. memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
  190. SH7753EVB_ETHERNET_MAC_SIZE);
  191. mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
  192. return 0;
  193. }
  194. static void init_ethernet_mac(void)
  195. {
  196. char mac_string[64];
  197. char env_string[64];
  198. int i;
  199. unsigned char *buf;
  200. buf = malloc(256);
  201. if (!buf) {
  202. printf("%s: malloc failed.\n", __func__);
  203. return;
  204. }
  205. get_sh_eth_mac_raw(buf, 256);
  206. /* Gigabit Ethernet */
  207. for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
  208. get_sh_eth_mac(i, mac_string, buf);
  209. if (i == 0)
  210. env_set("ethaddr", mac_string);
  211. else {
  212. sprintf(env_string, "eth%daddr", i);
  213. env_set(env_string, mac_string);
  214. }
  215. set_mac_to_sh_giga_eth_register(i, mac_string);
  216. }
  217. free(buf);
  218. }
  219. int board_late_init(void)
  220. {
  221. init_ethernet_mac();
  222. return 0;
  223. }
  224. #ifdef CONFIG_DEPRECATED
  225. int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  226. {
  227. int i, ret;
  228. char mac_string[256];
  229. struct spi_flash *spi;
  230. unsigned char *buf;
  231. if (argc != 3) {
  232. buf = malloc(256);
  233. if (!buf) {
  234. printf("%s: malloc failed.\n", __func__);
  235. return 1;
  236. }
  237. get_sh_eth_mac_raw(buf, 256);
  238. /* print current MAC address */
  239. for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
  240. get_sh_eth_mac(i, mac_string, buf);
  241. printf("GETHERC ch%d = %s\n", i, mac_string);
  242. }
  243. free(buf);
  244. return 0;
  245. }
  246. /* new setting */
  247. memset(mac_string, 0xff, sizeof(mac_string));
  248. sprintf(mac_string, "%s\t%s",
  249. argv[1], argv[2]);
  250. /* write MAC data to SPI rom */
  251. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  252. if (!spi) {
  253. printf("%s: spi_flash probe failed.\n", __func__);
  254. return 1;
  255. }
  256. ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
  257. SH7753EVB_SPI_SECTOR_SIZE);
  258. if (ret) {
  259. printf("%s: spi_flash erase failed.\n", __func__);
  260. return 1;
  261. }
  262. ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
  263. sizeof(mac_string), mac_string);
  264. if (ret) {
  265. printf("%s: spi_flash write failed.\n", __func__);
  266. spi_flash_free(spi);
  267. return 1;
  268. }
  269. spi_flash_free(spi);
  270. puts("The writing of the MAC address to SPI ROM was completed.\n");
  271. return 0;
  272. }
  273. U_BOOT_CMD(
  274. write_mac, 3, 1, do_write_mac,
  275. "write MAC address for GETHERC",
  276. "[GETHERC ch0] [GETHERC ch1]\n"
  277. );
  278. #endif