lowlevel_init.S 9.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013 Renesas Solutions Corp.
  4. */
  5. #include <config.h>
  6. #include <asm/processor.h>
  7. #include <asm/macro.h>
  8. .macro or32, addr, data
  9. mov.l \addr, r1
  10. mov.l \data, r0
  11. mov.l @r1, r2
  12. or r2, r0
  13. mov.l r0, @r1
  14. .endm
  15. .macro wait_DBCMD
  16. mov.l DBWAIT_A, r0
  17. mov.l @r0, r1
  18. .endm
  19. .global lowlevel_init
  20. .section .spiboot1.text
  21. .align 2
  22. lowlevel_init:
  23. mov #0, r14
  24. mova 2f, r0
  25. mov.l PC_MASK, r1
  26. tst r0, r1
  27. bf 2f
  28. bra exit_pmb
  29. nop
  30. .align 2
  31. /* If CPU runs on SDRAM (PC=0x5???????) or not. */
  32. PC_MASK: .long 0x20000000
  33. 2:
  34. mov #1, r14
  35. mov.l EXPEVT_A, r0
  36. mov.l @r0, r0
  37. mov.l EXPEVT_POWER_ON_RESET, r1
  38. cmp/eq r0, r1
  39. bt 1f
  40. /*
  41. * If EXPEVT value is manual reset or tlb multipul-hit,
  42. * initialization of DBSC3 is not necessary.
  43. */
  44. bra exit_ddr
  45. nop
  46. 1:
  47. /*------- Reset -------*/
  48. write32 MRSTCR0_A, MRSTCR0_D
  49. write32 MRSTCR1_A, MRSTCR1_D
  50. /* For Core Reset */
  51. mov.l DBACEN_A, r0
  52. mov.l @r0, r0
  53. cmp/eq #0, r0
  54. bt 3f
  55. /*
  56. * If DBACEN == 1(DBSC was already enabled), we have to avoid the
  57. * initialization of DDR3-SDRAM.
  58. */
  59. bra exit_ddr
  60. nop
  61. 3:
  62. /*------- DBSC3 -------*/
  63. /* oscillation stabilization time */
  64. wait_timer WAIT_OSC_TIME
  65. /* step 3 */
  66. write32 DBKIND_A, DBKIND_D
  67. /* step 4 */
  68. write32 DBCONF_A, DBCONF_D
  69. write32 DBTR0_A, DBTR0_D
  70. write32 DBTR1_A, DBTR1_D
  71. write32 DBTR2_A, DBTR2_D
  72. write32 DBTR3_A, DBTR3_D
  73. write32 DBTR4_A, DBTR4_D
  74. write32 DBTR5_A, DBTR5_D
  75. write32 DBTR6_A, DBTR6_D
  76. write32 DBTR7_A, DBTR7_D
  77. write32 DBTR8_A, DBTR8_D
  78. write32 DBTR9_A, DBTR9_D
  79. write32 DBTR10_A, DBTR10_D
  80. write32 DBTR11_A, DBTR11_D
  81. write32 DBTR12_A, DBTR12_D
  82. write32 DBTR13_A, DBTR13_D
  83. write32 DBTR14_A, DBTR14_D
  84. write32 DBTR15_A, DBTR15_D
  85. write32 DBTR16_A, DBTR16_D
  86. write32 DBTR17_A, DBTR17_D
  87. write32 DBTR18_A, DBTR18_D
  88. write32 DBTR19_A, DBTR19_D
  89. write32 DBRNK0_A, DBRNK0_D
  90. write32 DBADJ0_A, DBADJ0_D
  91. write32 DBADJ2_A, DBADJ2_D
  92. /* step 5 */
  93. write32 DBCMD_A, DBCMD_RSTL_VAL
  94. wait_timer WAIT_30US
  95. /* step 6 */
  96. write32 DBCMD_A, DBCMD_PDEN_VAL
  97. /* step 7 */
  98. write32 DBPDCNT3_A, DBPDCNT3_D
  99. /* step 8 */
  100. write32 DBPDCNT1_A, DBPDCNT1_D
  101. write32 DBPDCNT2_A, DBPDCNT2_D
  102. write32 DBPDLCK_A, DBPDLCK_D
  103. write32 DBPDRGA_A, DBPDRGA_D
  104. write32 DBPDRGD_A, DBPDRGD_D
  105. /* step 9 */
  106. wait_timer WAIT_30US
  107. /* step 10 */
  108. write32 DBPDCNT0_A, DBPDCNT0_D
  109. /* step 11 */
  110. wait_timer WAIT_30US
  111. wait_timer WAIT_30US
  112. /* step 12 */
  113. write32 DBCMD_A, DBCMD_WAIT_VAL
  114. wait_DBCMD
  115. /* step 13 */
  116. write32 DBCMD_A, DBCMD_RSTH_VAL
  117. wait_DBCMD
  118. /* step 14 */
  119. write32 DBCMD_A, DBCMD_WAIT_VAL
  120. write32 DBCMD_A, DBCMD_WAIT_VAL
  121. write32 DBCMD_A, DBCMD_WAIT_VAL
  122. write32 DBCMD_A, DBCMD_WAIT_VAL
  123. /* step 15 */
  124. write32 DBCMD_A, DBCMD_PDXT_VAL
  125. /* step 16 */
  126. write32 DBCMD_A, DBCMD_MRS2_VAL
  127. /* step 17 */
  128. write32 DBCMD_A, DBCMD_MRS3_VAL
  129. /* step 18 */
  130. write32 DBCMD_A, DBCMD_MRS1_VAL
  131. /* step 19 */
  132. write32 DBCMD_A, DBCMD_MRS0_VAL
  133. write32 DBPDNCNF_A, DBPDNCNF_D
  134. /* step 20 */
  135. write32 DBCMD_A, DBCMD_ZQCL_VAL
  136. write32 DBCMD_A, DBCMD_REF_VAL
  137. write32 DBCMD_A, DBCMD_REF_VAL
  138. wait_DBCMD
  139. /* step 21 */
  140. write32 DBCALTR_A, DBCALTR_D
  141. /* step 22 */
  142. write32 DBRFCNF0_A, DBRFCNF0_D
  143. write32 DBRFCNF1_A, DBRFCNF1_D
  144. write32 DBRFCNF2_A, DBRFCNF2_D
  145. /* step 23 */
  146. write32 DBCALCNF_A, DBCALCNF_D
  147. /* step 24 */
  148. write32 DBRFEN_A, DBRFEN_D
  149. write32 DBCMD_A, DBCMD_SRXT_VAL
  150. /* step 25 */
  151. write32 DBACEN_A, DBACEN_D
  152. /* step 26 */
  153. wait_DBCMD
  154. bra exit_ddr
  155. nop
  156. .align 2
  157. EXPEVT_A: .long 0xff000024
  158. EXPEVT_POWER_ON_RESET: .long 0x00000000
  159. /*------- Reset -------*/
  160. MRSTCR0_A: .long 0xffd50030
  161. MRSTCR0_D: .long 0xfe1ffe7f
  162. MRSTCR1_A: .long 0xffd50034
  163. MRSTCR1_D: .long 0xfff3ffff
  164. /*------- DBSC3 -------*/
  165. DBCMD_A: .long 0xfe800018
  166. DBKIND_A: .long 0xfe800020
  167. DBCONF_A: .long 0xfe800024
  168. DBTR0_A: .long 0xfe800040
  169. DBTR1_A: .long 0xfe800044
  170. DBTR2_A: .long 0xfe800048
  171. DBTR3_A: .long 0xfe800050
  172. DBTR4_A: .long 0xfe800054
  173. DBTR5_A: .long 0xfe800058
  174. DBTR6_A: .long 0xfe80005c
  175. DBTR7_A: .long 0xfe800060
  176. DBTR8_A: .long 0xfe800064
  177. DBTR9_A: .long 0xfe800068
  178. DBTR10_A: .long 0xfe80006c
  179. DBTR11_A: .long 0xfe800070
  180. DBTR12_A: .long 0xfe800074
  181. DBTR13_A: .long 0xfe800078
  182. DBTR14_A: .long 0xfe80007c
  183. DBTR15_A: .long 0xfe800080
  184. DBTR16_A: .long 0xfe800084
  185. DBTR17_A: .long 0xfe800088
  186. DBTR18_A: .long 0xfe80008c
  187. DBTR19_A: .long 0xfe800090
  188. DBRNK0_A: .long 0xfe800100
  189. DBPDCNT0_A: .long 0xfe800200
  190. DBPDCNT1_A: .long 0xfe800204
  191. DBPDCNT2_A: .long 0xfe800208
  192. DBPDCNT3_A: .long 0xfe80020c
  193. DBPDLCK_A: .long 0xfe800280
  194. DBPDRGA_A: .long 0xfe800290
  195. DBPDRGD_A: .long 0xfe8002a0
  196. DBADJ0_A: .long 0xfe8000c0
  197. DBADJ2_A: .long 0xfe8000c8
  198. DBRFCNF0_A: .long 0xfe8000e0
  199. DBRFCNF1_A: .long 0xfe8000e4
  200. DBRFCNF2_A: .long 0xfe8000e8
  201. DBCALCNF_A: .long 0xfe8000f4
  202. DBRFEN_A: .long 0xfe800014
  203. DBACEN_A: .long 0xfe800010
  204. DBWAIT_A: .long 0xfe80001c
  205. DBCALTR_A: .long 0xfe8000f8
  206. DBPDNCNF_A: .long 0xfe800180
  207. WAIT_OSC_TIME: .long 6000
  208. WAIT_30US: .long 13333
  209. DBCMD_RSTL_VAL: .long 0x20000000
  210. DBCMD_PDEN_VAL: .long 0x1000d73c
  211. DBCMD_WAIT_VAL: .long 0x0000d73c
  212. DBCMD_RSTH_VAL: .long 0x2100d73c
  213. DBCMD_PDXT_VAL: .long 0x110000c8
  214. DBCMD_MRS0_VAL: .long 0x28000930
  215. DBCMD_MRS1_VAL: .long 0x29000004
  216. DBCMD_MRS2_VAL: .long 0x2a000008
  217. DBCMD_MRS3_VAL: .long 0x2b000000
  218. DBCMD_ZQCL_VAL: .long 0x03000200
  219. DBCMD_REF_VAL: .long 0x0c000000
  220. DBCMD_SRXT_VAL: .long 0x19000000
  221. DBKIND_D: .long 0x00000007
  222. DBCONF_D: .long 0x0f030a01
  223. DBTR0_D: .long 0x00000007
  224. DBTR1_D: .long 0x00000006
  225. DBTR2_D: .long 0x00000000
  226. DBTR3_D: .long 0x00000007
  227. DBTR4_D: .long 0x00070007
  228. DBTR5_D: .long 0x0000001b
  229. DBTR6_D: .long 0x00000014
  230. DBTR7_D: .long 0x00000004
  231. DBTR8_D: .long 0x00000014
  232. DBTR9_D: .long 0x00000004
  233. DBTR10_D: .long 0x00000008
  234. DBTR11_D: .long 0x00000007
  235. DBTR12_D: .long 0x0000000e
  236. DBTR13_D: .long 0x000000a0
  237. DBTR14_D: .long 0x00060006
  238. DBTR15_D: .long 0x00000003
  239. DBTR16_D: .long 0x00160002
  240. DBTR17_D: .long 0x000c0000
  241. DBTR18_D: .long 0x00000200
  242. DBTR19_D: .long 0x00000040
  243. DBRNK0_D: .long 0x00000001
  244. DBPDCNT0_D: .long 0x00000001
  245. DBPDCNT1_D: .long 0x00000001
  246. DBPDCNT2_D: .long 0x00000000
  247. DBPDCNT3_D: .long 0x00004010
  248. DBPDLCK_D: .long 0x0000a55a
  249. DBPDRGA_D: .long 0x00000028
  250. DBPDRGD_D: .long 0x00017100
  251. DBADJ0_D: .long 0x00010000
  252. DBADJ2_D: .long 0x18061806
  253. DBRFCNF0_D: .long 0x000001ff
  254. DBRFCNF1_D: .long 0x00081040
  255. DBRFCNF2_D: .long 0x00000000
  256. DBCALCNF_D: .long 0x0000ffff
  257. DBRFEN_D: .long 0x00000001
  258. DBACEN_D: .long 0x00000001
  259. DBCALTR_D: .long 0x08200820
  260. DBPDNCNF_D: .long 0x00000001
  261. .align 2
  262. exit_ddr:
  263. #if defined(CONFIG_SH_32BIT)
  264. /*------- set PMB -------*/
  265. write32 PASCR_A, PASCR_29BIT_D
  266. write32 MMUCR_A, MMUCR_D
  267. /*****************************************************************
  268. * ent virt phys v sz c wt
  269. * 0 0xa0000000 0x00000000 1 128M 0 1
  270. * 1 0xa8000000 0x48000000 1 128M 0 1
  271. * 5 0x88000000 0x48000000 1 128M 1 1
  272. */
  273. write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
  274. write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
  275. write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
  276. write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
  277. write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
  278. write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
  279. write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
  280. write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
  281. write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
  282. write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
  283. write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
  284. write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
  285. write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
  286. write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
  287. write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
  288. write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
  289. write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
  290. write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
  291. write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
  292. write32 PASCR_A, PASCR_INIT
  293. mov.l DUMMY_ADDR, r0
  294. icbi @r0
  295. #endif /* if defined(CONFIG_SH_32BIT) */
  296. exit_pmb:
  297. /* CPU is running on ILRAM? */
  298. mov r14, r0
  299. tst #1, r0
  300. bt 1f
  301. mov.l _stack_ilram, r15
  302. mov.l _spiboot_main, r0
  303. 100: bsrf r0
  304. nop
  305. .align 2
  306. _spiboot_main: .long (spiboot_main - (100b + 4))
  307. _stack_ilram: .long 0xe5204000
  308. 1:
  309. write32 CCR_A, CCR_D
  310. rts
  311. nop
  312. .align 2
  313. #if defined(CONFIG_SH_32BIT)
  314. /*------- set PMB -------*/
  315. PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
  316. PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
  317. PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
  318. PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
  319. PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
  320. PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
  321. PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
  322. PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
  323. PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
  324. PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
  325. PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
  326. PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
  327. PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
  328. PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
  329. PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
  330. PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
  331. PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
  332. PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
  333. PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
  334. PMB_ADDR_NOT_USE_D: .long 0x00000000
  335. PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
  336. PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
  337. PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
  338. /* ppn ub v s1 s0 c wt */
  339. PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
  340. PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
  341. PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
  342. PASCR_A: .long 0xff000070
  343. DUMMY_ADDR: .long 0xa0000000
  344. PASCR_29BIT_D: .long 0x00000000
  345. PASCR_INIT: .long 0x80000080
  346. MMUCR_A: .long 0xff000010
  347. MMUCR_D: .long 0x00000004 /* clear ITLB */
  348. #endif /* CONFIG_SH_32BIT */
  349. CCR_A: .long CCR
  350. CCR_D: .long CCR_CACHE_INIT