kwbimage.cfg 5.0 KB

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  1. # SPDX-License-Identifier: GPL-2.0+
  2. #
  3. # Copyright (C) 2011-2012
  4. # Gerald Kerma <dreagle@doukki.net>
  5. # Simon Baatz <gmbnomis@gmail.com>
  6. # Luka Perkov <luka@openwrt.org>
  7. # Refer doc/README.kwbimage for more details about how-to configure
  8. # and create kirkwood boot image
  9. #
  10. # Boot Media configurations
  11. BOOT_FROM nand
  12. NAND_ECC_MODE default
  13. NAND_PAGE_SIZE 0x0800
  14. # SOC registers configuration using bootrom header extension
  15. # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
  16. # Configure RGMII-0 interface pad voltage to 1.8V
  17. DATA 0xffd100e0 0x1b1b1b9b
  18. # Dram initalization for SINGLE x16 CL=5 @ 400MHz
  19. DATA 0xffd01400 0x43000c30 # DDR Configuration register
  20. # bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
  21. # bit23-14: 0x0,
  22. # bit24: 0x1, enable exit self refresh mode on DDR access
  23. # bit25: 0x1, required
  24. # bit29-26: 0x0,
  25. # bit31-30: 0x1,
  26. DATA 0xffd01404 0x37543000 # DDR Controller Control Low
  27. # bit4: 0x0, addr/cmd in smame cycle
  28. # bit5: 0x0, clk is driven during self refresh, we don't care for APX
  29. # bit6: 0x0, use recommended falling edge of clk for addr/cmd
  30. # bit14: 0x0, input buffer always powered up
  31. # bit18: 0x1, cpu lock transaction enabled
  32. # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
  33. # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
  34. # bit30-28: 0x3, required
  35. # bit31: 0x0, no additional STARTBURST delay
  36. DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
  37. # bit3-0: TRAS lsbs
  38. # bit7-4: TRCD
  39. # bit11-8: TRP
  40. # bit15-12: TWR
  41. # bit19-16: TWTR
  42. # bit20: TRAS msb
  43. # bit23-21: 0x0
  44. # bit27-24: TRRD
  45. # bit31-28: TRTP
  46. DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
  47. # bit6-0: TRFC
  48. # bit8-7: TR2R
  49. # bit10-9: TR2W
  50. # bit12-11: TW2W
  51. # bit31-13: 0x0, required
  52. DATA 0xffd01410 0x0000000c # DDR Address Control
  53. # bit1-0: 00, Cs0width (x8)
  54. # bit3-2: 11, Cs0size (1Gb)
  55. # bit5-4: 00, Cs1width (x8)
  56. # bit7-6: 11, Cs1size (1Gb)
  57. # bit9-8: 00, Cs2width (nonexistent)
  58. # bit11-10: 00, Cs2size (nonexistent)
  59. # bit13-12: 00, Cs3width (nonexistent)
  60. # bit15-14: 00, Cs3size (nonexistent)
  61. # bit16: 0, Cs0AddrSel
  62. # bit17: 0, Cs1AddrSel
  63. # bit18: 0, Cs2AddrSel
  64. # bit19: 0, Cs3AddrSel
  65. # bit31-20: 0x0, required
  66. DATA 0xffd01414 0x00000000 # DDR Open Pages Control
  67. # bit0: 0, OpenPage enabled
  68. # bit31-1: 0x0, required
  69. DATA 0xffd01418 0x00000000 # DDR Operation
  70. # bit3-0: 0x0, DDR cmd
  71. # bit31-4: 0x0, required
  72. DATA 0xffd0141c 0x00000c52 # DDR Mode
  73. # bit2-0: 0x2, BurstLen=2 required
  74. # bit3: 0x0, BurstType=0 required
  75. # bit6-4: 0x4, CL=5
  76. # bit7: 0x0, TestMode=0 normal
  77. # bit8: 0x0, DLL reset=0 normal
  78. # bit11-9: 0x6, auto-precharge write recovery
  79. # bit12: 0x0, PD must be zero
  80. # bit31-13: 0x0, required
  81. DATA 0xffd01420 0x00000040 # DDR Extended Mode
  82. # bit0: 0, DDR DLL enabled
  83. # bit1: 0, DDR drive strenght normal
  84. # bit2: 1, DDR ODT control lsd (disabled)
  85. # bit5-3: 0x0, required
  86. # bit6: 0, DDR ODT control msb, (disabled)
  87. # bit9-7: 0x0, required
  88. # bit10: 0, differential DQS enabled
  89. # bit11: 0, required
  90. # bit12: 0, DDR output buffer enabled
  91. # bit31-13: 0x0, required
  92. DATA 0xffd01424 0x0000f17f # DDR Controller Control High
  93. # bit2-0: 0x7, required
  94. # bit3: 0x1, MBUS Burst Chop disabled
  95. # bit6-4: 0x7, required
  96. # bit7: 0x0,
  97. # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
  98. # bit9: 0x0, no half clock cycle addition to dataout
  99. # bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
  100. # bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
  101. # bit15-12: 0xf, required
  102. # bit31-16: 0, required
  103. DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
  104. DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
  105. DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
  106. DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
  107. # bit0: 0x1, Window enabled
  108. # bit1: 0x0, Write Protect disabled
  109. # bit3-2: 0x0, CS0 hit selected
  110. # bit23-4: 0xfffff, required
  111. # bit31-24: 0x0f, Size (i.e. 256MB)
  112. DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb
  113. DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
  114. DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
  115. DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
  116. DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
  117. # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
  118. # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
  119. # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
  120. # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
  121. DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
  122. # bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
  123. # bit3-2: 0x1, ODT1 active NEVER!
  124. # bit31-4: 0x0, required
  125. DATA 0xffd0149c 0x0000e803 # CPU ODT Control
  126. DATA 0xffd01480 0x00000001 # DDR Initialization Control
  127. # bit0: 0x1, enable DDR init upon this register write
  128. DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register
  129. DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register
  130. # End of Header extension
  131. DATA 0x0 0x0