ap143.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/io.h>
  8. #include <asm/addrspace.h>
  9. #include <asm/types.h>
  10. #include <mach/ar71xx_regs.h>
  11. #include <mach/ddr.h>
  12. #include <mach/ath79.h>
  13. #include <debug_uart.h>
  14. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  15. void board_debug_uart_init(void)
  16. {
  17. void __iomem *regs;
  18. u32 val;
  19. regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
  20. MAP_NOCACHE);
  21. /*
  22. * GPIO9 as input, GPIO10 as output
  23. */
  24. val = readl(regs + AR71XX_GPIO_REG_OE);
  25. val |= QCA953X_GPIO(9);
  26. val &= ~QCA953X_GPIO(10);
  27. writel(val, regs + AR71XX_GPIO_REG_OE);
  28. /*
  29. * Enable GPIO10 as UART0_SOUT
  30. */
  31. val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
  32. val &= ~QCA953X_GPIO_MUX_MASK(16);
  33. val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
  34. writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
  35. /*
  36. * Enable GPIO9 as UART0_SIN
  37. */
  38. val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
  39. val &= ~QCA953X_GPIO_MUX_MASK(8);
  40. val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
  41. writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
  42. /*
  43. * Enable GPIO10 output
  44. */
  45. val = readl(regs + AR71XX_GPIO_REG_OUT);
  46. val |= QCA953X_GPIO(10);
  47. writel(val, regs + AR71XX_GPIO_REG_OUT);
  48. }
  49. #endif
  50. int board_early_init_f(void)
  51. {
  52. ddr_init();
  53. ath79_eth_reset();
  54. return 0;
  55. }