spl.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
  4. * Author: Teresa Remmet <t.remmet@phytec.de>
  5. */
  6. #include <common.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/ddr.h>
  9. #include <asm/arch/imx8mm_pins.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/mach-imx/boot_mode.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <dm/device.h>
  14. #include <dm/uclass.h>
  15. #include <hang.h>
  16. #include <init.h>
  17. #include <log.h>
  18. #include <spl.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. int spl_board_boot_device(enum boot_device boot_dev_spl)
  21. {
  22. switch (boot_dev_spl) {
  23. case SD2_BOOT:
  24. case MMC2_BOOT:
  25. return BOOT_DEVICE_MMC1;
  26. case SD3_BOOT:
  27. case MMC3_BOOT:
  28. return BOOT_DEVICE_MMC2;
  29. case QSPI_BOOT:
  30. return BOOT_DEVICE_NOR;
  31. case USB_BOOT:
  32. return BOOT_DEVICE_BOARD;
  33. default:
  34. return BOOT_DEVICE_NONE;
  35. }
  36. }
  37. void spl_dram_init(void)
  38. {
  39. ddr_init(&dram_timing);
  40. }
  41. void spl_board_init(void)
  42. {
  43. /* Serial download mode */
  44. if (is_usb_boot()) {
  45. puts("Back to ROM, SDP\n");
  46. restore_boot_params();
  47. }
  48. puts("Normal Boot\n");
  49. }
  50. #ifdef CONFIG_SPL_LOAD_FIT
  51. int board_fit_config_name_match(const char *name)
  52. {
  53. /* Just empty function now - can't decide what to choose */
  54. debug("%s: %s\n", __func__, name);
  55. return 0;
  56. }
  57. #endif
  58. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  59. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
  60. static iomux_v3_cfg_t const uart_pads[] = {
  61. IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  62. IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  63. };
  64. static iomux_v3_cfg_t const wdog_pads[] = {
  65. IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  66. };
  67. int board_early_init_f(void)
  68. {
  69. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  70. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  71. set_wdog_reset(wdog);
  72. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  73. return 0;
  74. }
  75. void board_init_f(ulong dummy)
  76. {
  77. struct udevice *dev;
  78. int ret;
  79. arch_cpu_init();
  80. init_uart_clk(2);
  81. board_early_init_f();
  82. timer_init();
  83. preloader_console_init();
  84. /* Clear the BSS. */
  85. memset(__bss_start, 0, __bss_end - __bss_start);
  86. ret = spl_early_init();
  87. if (ret) {
  88. debug("spl_early_init() failed: %d\n", ret);
  89. hang();
  90. }
  91. ret = uclass_get_device_by_name(UCLASS_CLK,
  92. "clock-controller@30380000", &dev);
  93. if (ret < 0) {
  94. printf("Failed to find clock node. Check device tree\n");
  95. hang();
  96. }
  97. enable_tzc380();
  98. /* DDR initialization */
  99. spl_dram_init();
  100. board_init_r(NULL, 0);
  101. }