board.c 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
  9. * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
  10. * Copyright (C) 2019 DENX Software Engineering GmbH
  11. */
  12. #include <common.h>
  13. #include <init.h>
  14. #include <spl.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/ddr_defs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <power/tps65910.h>
  20. #include <jffs2/load_kernel.h>
  21. #include <mtd_node.h>
  22. #include <fdt_support.h>
  23. #include "board.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #ifdef CONFIG_SPL_BUILD
  26. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  27. /* DDR RAM defines */
  28. #define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */
  29. #define OSC (V_OSCK / 1000000)
  30. const struct dpll_params dpll_ddr = {
  31. DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
  32. const struct dpll_params *get_dpll_ddr_params(void)
  33. {
  34. return &dpll_ddr;
  35. }
  36. const struct ctrl_ioregs ioregs = {
  37. .cm0ioctl = 0x18B,
  38. .cm1ioctl = 0x18B,
  39. .cm2ioctl = 0x18B,
  40. .dt0ioctl = 0x18B,
  41. .dt1ioctl = 0x18B,
  42. };
  43. static const struct cmd_control ddr3_cmd_ctrl_data = {
  44. .cmd0csratio = 0x80,
  45. .cmd0iclkout = 0x0,
  46. .cmd1csratio = 0x80,
  47. .cmd1iclkout = 0x0,
  48. .cmd2csratio = 0x80,
  49. .cmd2iclkout = 0x0,
  50. };
  51. enum {
  52. PHYCORE_R2_MT41K128M16JT_256MB,
  53. PHYCORE_R2_MT41K256M16TW107IT_512MB,
  54. PHYCORE_R2_MT41K512M16HA125IT_1024MB,
  55. };
  56. struct am335x_sdram_timings {
  57. struct emif_regs ddr3_emif_reg_data;
  58. struct ddr_data ddr3_data;
  59. };
  60. static struct am335x_sdram_timings physom_timings[] = {
  61. [PHYCORE_R2_MT41K128M16JT_256MB] = {
  62. .ddr3_emif_reg_data = {
  63. .sdram_config = 0x61C052B2,
  64. .ref_ctrl = 0x00000C30,
  65. .sdram_tim1 = 0x0AAAD4DB,
  66. .sdram_tim2 = 0x26437FDA,
  67. .sdram_tim3 = 0x501F83FF,
  68. .zq_config = 0x50074BE4,
  69. .emif_ddr_phy_ctlr_1 = 0x7,
  70. .ocp_config = 0x003d3d3d,
  71. },
  72. .ddr3_data = {
  73. .datardsratio0 = 0x36,
  74. .datawdsratio0 = 0x38,
  75. .datafwsratio0 = 0x99,
  76. .datawrsratio0 = 0x73,
  77. },
  78. },
  79. [PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
  80. .ddr3_emif_reg_data = {
  81. .sdram_config = 0x61C05332,
  82. .ref_ctrl = 0x00000C30,
  83. .sdram_tim1 = 0x0AAAD4DB,
  84. .sdram_tim2 = 0x266B7FDA,
  85. .sdram_tim3 = 0x501F867F,
  86. .zq_config = 0x50074BE4,
  87. .emif_ddr_phy_ctlr_1 = 0x7,
  88. .ocp_config = 0x003d3d3d,
  89. },
  90. .ddr3_data = {
  91. .datardsratio0 = 0x37,
  92. .datawdsratio0 = 0x38,
  93. .datafwsratio0 = 0x92,
  94. .datawrsratio0 = 0x72,
  95. },
  96. },
  97. [PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
  98. .ddr3_emif_reg_data = {
  99. .sdram_config = 0x61C053B2,
  100. .ref_ctrl = 0x00000C30,
  101. .sdram_tim1 = 0x0AAAD4DB,
  102. .sdram_tim2 = 0x268F7FDA,
  103. .sdram_tim3 = 0x501F88BF,
  104. .zq_config = 0x50074BE4,
  105. .emif_ddr_phy_ctlr_1 = 0x7,
  106. .ocp_config = 0x003d3d3d,
  107. },
  108. .ddr3_data = {
  109. .datardsratio0 = 0x38,
  110. .datawdsratio0 = 0x4d,
  111. .datafwsratio0 = 0x9d,
  112. .datawrsratio0 = 0x82,
  113. },
  114. },
  115. };
  116. void sdram_init(void)
  117. {
  118. /* Configure memory to maximum supported size for detection */
  119. int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
  120. config_ddr(DDR_CLK_MHZ, &ioregs,
  121. &physom_timings[ram_type_index].ddr3_data,
  122. &ddr3_cmd_ctrl_data,
  123. &physom_timings[ram_type_index].ddr3_emif_reg_data,
  124. 0);
  125. /* Detect memory physically present */
  126. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  127. CONFIG_MAX_RAM_BANK_SIZE);
  128. /* Reconfigure memory for actual detected size */
  129. switch (gd->ram_size) {
  130. case SZ_1G:
  131. ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
  132. break;
  133. case SZ_512M:
  134. ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
  135. break;
  136. case SZ_256M:
  137. default:
  138. ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
  139. break;
  140. }
  141. config_ddr(DDR_CLK_MHZ, &ioregs,
  142. &physom_timings[ram_type_index].ddr3_data,
  143. &ddr3_cmd_ctrl_data,
  144. &physom_timings[ram_type_index].ddr3_emif_reg_data,
  145. 0);
  146. }
  147. const struct dpll_params *get_dpll_mpu_params(void)
  148. {
  149. int ind = get_sys_clk_index();
  150. int freq = am335x_get_efuse_mpu_max_freq(cdev);
  151. switch (freq) {
  152. case MPUPLL_M_1000:
  153. return &dpll_mpu_opp[ind][5];
  154. case MPUPLL_M_800:
  155. return &dpll_mpu_opp[ind][4];
  156. case MPUPLL_M_720:
  157. return &dpll_mpu_opp[ind][3];
  158. case MPUPLL_M_600:
  159. return &dpll_mpu_opp[ind][2];
  160. case MPUPLL_M_500:
  161. return &dpll_mpu_opp100;
  162. case MPUPLL_M_300:
  163. return &dpll_mpu_opp[ind][0];
  164. }
  165. return &dpll_mpu_opp[ind][0];
  166. }
  167. static void scale_vcores_generic(int freq)
  168. {
  169. int sil_rev, mpu_vdd;
  170. /*
  171. * We use a TPS65910 PMIC. For all MPU frequencies we support we use a
  172. * CORE voltage of 1.10V. For MPU voltage we need to switch based on
  173. * the frequency we are running at.
  174. */
  175. if (power_tps65910_init(0))
  176. return;
  177. /*
  178. * Depending on MPU clock and PG we will need a different
  179. * VDD to drive at that speed.
  180. */
  181. sil_rev = readl(&cdev->deviceid) >> 28;
  182. mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
  183. /* Tell the TPS65910 to use i2c */
  184. tps65910_set_i2c_control();
  185. /* First update MPU voltage. */
  186. if (tps65910_voltage_update(MPU, mpu_vdd))
  187. return;
  188. /* Second, update the CORE voltage. */
  189. if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
  190. return;
  191. }
  192. void scale_vcores(void)
  193. {
  194. int freq;
  195. freq = am335x_get_efuse_mpu_max_freq(cdev);
  196. scale_vcores_generic(freq);
  197. }
  198. void set_uart_mux_conf(void)
  199. {
  200. enable_uart0_pin_mux();
  201. }
  202. void set_mux_conf_regs(void)
  203. {
  204. enable_i2c0_pin_mux();
  205. enable_board_pin_mux();
  206. }
  207. #endif
  208. /*
  209. * Basic board specific setup. Pinmux has been handled already.
  210. */
  211. int board_init(void)
  212. {
  213. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  214. return 0;
  215. }
  216. #ifdef CONFIG_OF_BOARD_SETUP
  217. int ft_board_setup(void *blob, struct bd_info *bd)
  218. {
  219. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  220. static const struct node_info nodes[] = {
  221. { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
  222. };
  223. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  224. #endif
  225. return 0;
  226. }
  227. #endif