pfla02.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <net.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/iomux.h>
  14. #include <asm/arch/crm_regs.h>
  15. #include <asm/arch/iomux.h>
  16. #include <asm/arch/mx6-pins.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/boot_mode.h>
  19. #include <asm/mach-imx/mxc_i2c.h>
  20. #include <asm/mach-imx/spi.h>
  21. #include <env.h>
  22. #include <linux/delay.h>
  23. #include <linux/errno.h>
  24. #include <asm/gpio.h>
  25. #include <mmc.h>
  26. #include <i2c.h>
  27. #include <fsl_esdhc_imx.h>
  28. #include <nand.h>
  29. #include <miiphy.h>
  30. #include <netdev.h>
  31. #include <asm/arch/sys_proto.h>
  32. #include <asm/sections.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  35. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  36. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  38. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  39. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  40. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  41. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  42. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  43. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  44. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  45. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  46. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  47. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  48. #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
  49. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  50. #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  51. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  52. #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
  53. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  54. #define GREEN_LED IMX_GPIO_NR(2, 31)
  55. #define RED_LED IMX_GPIO_NR(1, 30)
  56. #define IMX6Q_DRIVE_STRENGTH 0x30
  57. int dram_init(void)
  58. {
  59. gd->ram_size = imx_ddr_size();
  60. return 0;
  61. }
  62. static iomux_v3_cfg_t const uart4_pads[] = {
  63. IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  64. IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  65. };
  66. static iomux_v3_cfg_t const enet_pads[] = {
  67. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  75. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  77. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  84. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85. IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86. };
  87. static iomux_v3_cfg_t const ecspi3_pads[] = {
  88. IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  89. IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  90. IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  91. IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92. };
  93. static iomux_v3_cfg_t const gpios_pads[] = {
  94. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95. IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96. IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97. IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  98. IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  99. IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  100. IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  101. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  102. };
  103. #if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
  104. /* NAND */
  105. static iomux_v3_cfg_t const nfc_pads[] = {
  106. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  107. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  108. IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  109. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  110. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  111. IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  112. IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  113. IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  114. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  115. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  116. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  117. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  118. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  119. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  120. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  121. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  122. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  123. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  124. IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL)),
  125. };
  126. #endif
  127. static struct i2c_pads_info i2c_pad_info = {
  128. .scl = {
  129. .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
  130. .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD,
  131. .gp = IMX_GPIO_NR(3, 21)
  132. },
  133. .sda = {
  134. .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
  135. .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD,
  136. .gp = IMX_GPIO_NR(3, 28)
  137. }
  138. };
  139. static struct fsl_esdhc_cfg usdhc_cfg[] = {
  140. {USDHC3_BASE_ADDR,
  141. .max_bus_width = 4},
  142. {.esdhc_base = USDHC2_BASE_ADDR,
  143. .max_bus_width = 4},
  144. };
  145. #if !defined(CONFIG_SPL_BUILD)
  146. static iomux_v3_cfg_t const usdhc2_pads[] = {
  147. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  148. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  149. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  150. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  151. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  152. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  153. IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  154. IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  155. };
  156. #endif
  157. static iomux_v3_cfg_t const usdhc3_pads[] = {
  158. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  159. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  160. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  161. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  162. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  163. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  164. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  165. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  166. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  167. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  168. };
  169. int board_mmc_get_env_dev(int devno)
  170. {
  171. return devno - 1;
  172. }
  173. int board_mmc_getcd(struct mmc *mmc)
  174. {
  175. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  176. int ret = 0;
  177. switch (cfg->esdhc_base) {
  178. case USDHC2_BASE_ADDR:
  179. ret = !gpio_get_value(USDHC2_CD_GPIO);
  180. ret = 1;
  181. break;
  182. case USDHC3_BASE_ADDR:
  183. ret = 1;
  184. break;
  185. }
  186. return ret;
  187. }
  188. #ifndef CONFIG_SPL_BUILD
  189. int board_mmc_init(struct bd_info *bis)
  190. {
  191. int ret;
  192. int i;
  193. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  194. switch (i) {
  195. case 0:
  196. SETUP_IOMUX_PADS(usdhc3_pads);
  197. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  198. break;
  199. case 1:
  200. SETUP_IOMUX_PADS(usdhc2_pads);
  201. gpio_direction_input(USDHC2_CD_GPIO);
  202. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  203. break;
  204. default:
  205. printf("Warning: you configured more USDHC controllers"
  206. "(%d) then supported by the board (%d)\n",
  207. i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  208. return -EINVAL;
  209. }
  210. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  211. if (ret)
  212. return ret;
  213. }
  214. return 0;
  215. }
  216. #endif
  217. static void setup_iomux_uart(void)
  218. {
  219. SETUP_IOMUX_PADS(uart4_pads);
  220. }
  221. static void setup_iomux_enet(void)
  222. {
  223. SETUP_IOMUX_PADS(enet_pads);
  224. gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
  225. mdelay(10);
  226. gpio_set_value(ENET_PHY_RESET_GPIO, 1);
  227. mdelay(30);
  228. }
  229. static void setup_spi(void)
  230. {
  231. gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
  232. gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
  233. SETUP_IOMUX_PADS(ecspi3_pads);
  234. enable_spi_clk(true, 2);
  235. }
  236. static void setup_gpios(void)
  237. {
  238. SETUP_IOMUX_PADS(gpios_pads);
  239. }
  240. #if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
  241. static void setup_gpmi_nand(void)
  242. {
  243. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  244. /* config gpmi nand iomux */
  245. SETUP_IOMUX_PADS(nfc_pads);
  246. /* gate ENFC_CLK_ROOT clock first,before clk source switch */
  247. clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  248. /* config gpmi and bch clock to 100 MHz */
  249. clrsetbits_le32(&mxc_ccm->cs2cdr,
  250. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  251. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  252. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  253. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  254. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  255. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  256. /* enable ENFC_CLK_ROOT clock */
  257. setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  258. /* enable gpmi and bch clock gating */
  259. setbits_le32(&mxc_ccm->CCGR4,
  260. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  261. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  262. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  263. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  264. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  265. /* enable apbh clock gating */
  266. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  267. }
  268. #endif
  269. /*
  270. * Board revision is coded in 4 GPIOs
  271. */
  272. u32 get_board_rev(void)
  273. {
  274. u32 rev;
  275. int i;
  276. for (i = 0, rev = 0; i < 4; i++)
  277. rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i);
  278. return 16 - rev;
  279. }
  280. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  281. {
  282. if (bus != 2 || (cs != 0))
  283. return -EINVAL;
  284. return IMX_GPIO_NR(4, 24);
  285. }
  286. int board_eth_init(struct bd_info *bis)
  287. {
  288. setup_iomux_enet();
  289. return cpu_eth_init(bis);
  290. }
  291. int board_early_init_f(void)
  292. {
  293. setup_iomux_uart();
  294. return 0;
  295. }
  296. int board_init(void)
  297. {
  298. /* address of boot parameters */
  299. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  300. #ifdef CONFIG_SYS_I2C_MXC
  301. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
  302. #endif
  303. #ifdef CONFIG_MXC_SPI
  304. setup_spi();
  305. #endif
  306. setup_gpios();
  307. #if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
  308. setup_gpmi_nand();
  309. #endif
  310. return 0;
  311. }
  312. #ifdef CONFIG_CMD_BMODE
  313. /*
  314. * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
  315. * see Table 8-11 and Table 5-9
  316. * BOOT_CFG1[7] = 1 (boot from NAND)
  317. * BOOT_CFG1[5] = 0 - raw NAND
  318. * BOOT_CFG1[4] = 0 - default pad settings
  319. * BOOT_CFG1[3:2] = 00 - devices = 1
  320. * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
  321. * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
  322. * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
  323. * BOOT_CFG2[0] = 0 - Reset time 12ms
  324. */
  325. static const struct boot_mode board_boot_modes[] = {
  326. /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
  327. {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
  328. {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  329. {NULL, 0},
  330. };
  331. #endif
  332. int board_late_init(void)
  333. {
  334. char buf[10];
  335. #ifdef CONFIG_CMD_BMODE
  336. add_board_boot_modes(board_boot_modes);
  337. #endif
  338. snprintf(buf, sizeof(buf), "%d", get_board_rev());
  339. env_set("board_rev", buf);
  340. return 0;
  341. }
  342. #ifdef CONFIG_SPL_BUILD
  343. #include <asm/arch/mx6-ddr.h>
  344. #include <spl.h>
  345. #include <linux/libfdt.h>
  346. #define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
  347. static void phyflex_err006282_workaround(void)
  348. {
  349. /*
  350. * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
  351. * to the CMIC. If this pin isn't toggled within 10s the boards
  352. * reset. The pin is unconnected on older boards, so we do not
  353. * need a check for older boards before applying this fixup.
  354. */
  355. gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
  356. mdelay(2);
  357. gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
  358. mdelay(2);
  359. gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
  360. gpio_direction_input(MX6_PHYFLEX_ERR006282);
  361. }
  362. static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  363. .dram_sdclk_0 = 0x00000030,
  364. .dram_sdclk_1 = 0x00000030,
  365. .dram_cas = 0x00000030,
  366. .dram_ras = 0x00000030,
  367. .dram_reset = 0x00000030,
  368. .dram_sdcke0 = 0x00003000,
  369. .dram_sdcke1 = 0x00003000,
  370. .dram_sdba2 = 0x00000030,
  371. .dram_sdodt0 = 0x00000030,
  372. .dram_sdodt1 = 0x00000030,
  373. .dram_sdqs0 = 0x00000028,
  374. .dram_sdqs1 = 0x00000028,
  375. .dram_sdqs2 = 0x00000028,
  376. .dram_sdqs3 = 0x00000028,
  377. .dram_sdqs4 = 0x00000028,
  378. .dram_sdqs5 = 0x00000028,
  379. .dram_sdqs6 = 0x00000028,
  380. .dram_sdqs7 = 0x00000028,
  381. .dram_dqm0 = 0x00000028,
  382. .dram_dqm1 = 0x00000028,
  383. .dram_dqm2 = 0x00000028,
  384. .dram_dqm3 = 0x00000028,
  385. .dram_dqm4 = 0x00000028,
  386. .dram_dqm5 = 0x00000028,
  387. .dram_dqm6 = 0x00000028,
  388. .dram_dqm7 = 0x00000028,
  389. };
  390. static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  391. .grp_ddr_type = 0x000C0000,
  392. .grp_ddrmode_ctl = 0x00020000,
  393. .grp_ddrpke = 0x00000000,
  394. .grp_addds = IMX6Q_DRIVE_STRENGTH,
  395. .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
  396. .grp_ddrmode = 0x00020000,
  397. .grp_b0ds = 0x00000028,
  398. .grp_b1ds = 0x00000028,
  399. .grp_b2ds = 0x00000028,
  400. .grp_b3ds = 0x00000028,
  401. .grp_b4ds = 0x00000028,
  402. .grp_b5ds = 0x00000028,
  403. .grp_b6ds = 0x00000028,
  404. .grp_b7ds = 0x00000028,
  405. };
  406. static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
  407. .p0_mpwldectrl0 = 0x00110011,
  408. .p0_mpwldectrl1 = 0x00240024,
  409. .p1_mpwldectrl0 = 0x00260038,
  410. .p1_mpwldectrl1 = 0x002C0038,
  411. .p0_mpdgctrl0 = 0x03400350,
  412. .p0_mpdgctrl1 = 0x03440340,
  413. .p1_mpdgctrl0 = 0x034C0354,
  414. .p1_mpdgctrl1 = 0x035C033C,
  415. .p0_mprddlctl = 0x322A2A2A,
  416. .p1_mprddlctl = 0x302C2834,
  417. .p0_mpwrdlctl = 0x34303834,
  418. .p1_mpwrdlctl = 0x422A3E36,
  419. };
  420. /* Index in RAM Chip array */
  421. enum {
  422. RAM_MT64K,
  423. RAM_MT128K,
  424. RAM_MT256K
  425. };
  426. static struct mx6_ddr3_cfg mt41k_xx[] = {
  427. /* MT41K64M16JT-125 (1Gb density) */
  428. {
  429. .mem_speed = 1600,
  430. .density = 1,
  431. .width = 16,
  432. .banks = 8,
  433. .rowaddr = 13,
  434. .coladdr = 10,
  435. .pagesz = 2,
  436. .trcd = 1375,
  437. .trcmin = 4875,
  438. .trasmin = 3500,
  439. .SRT = 1,
  440. },
  441. /* MT41K256M16JT-125 (2Gb density) */
  442. {
  443. .mem_speed = 1600,
  444. .density = 2,
  445. .width = 16,
  446. .banks = 8,
  447. .rowaddr = 14,
  448. .coladdr = 10,
  449. .pagesz = 2,
  450. .trcd = 1375,
  451. .trcmin = 4875,
  452. .trasmin = 3500,
  453. .SRT = 1,
  454. },
  455. /* MT41K256M16JT-125 (4Gb density) */
  456. {
  457. .mem_speed = 1600,
  458. .density = 4,
  459. .width = 16,
  460. .banks = 8,
  461. .rowaddr = 15,
  462. .coladdr = 10,
  463. .pagesz = 2,
  464. .trcd = 1375,
  465. .trcmin = 4875,
  466. .trasmin = 3500,
  467. .SRT = 1,
  468. }
  469. };
  470. static void ccgr_init(void)
  471. {
  472. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  473. writel(0x00C03F3F, &ccm->CCGR0);
  474. writel(0x0030FC03, &ccm->CCGR1);
  475. writel(0x0FFFC000, &ccm->CCGR2);
  476. writel(0x3FF00000, &ccm->CCGR3);
  477. writel(0x00FFF300, &ccm->CCGR4);
  478. writel(0x0F0000C3, &ccm->CCGR5);
  479. writel(0x000003FF, &ccm->CCGR6);
  480. }
  481. static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
  482. struct mx6_ddr3_cfg *mem_ddr)
  483. {
  484. mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  485. mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
  486. }
  487. int board_mmc_init(struct bd_info *bis)
  488. {
  489. if (spl_boot_device() == BOOT_DEVICE_SPI)
  490. printf("MMC SEtup, Boot SPI");
  491. SETUP_IOMUX_PADS(usdhc3_pads);
  492. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  493. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  494. usdhc_cfg[0].max_bus_width = 4;
  495. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  496. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  497. }
  498. void board_boot_order(u32 *spl_boot_list)
  499. {
  500. spl_boot_list[0] = spl_boot_device();
  501. printf("Boot device %x\n", spl_boot_list[0]);
  502. switch (spl_boot_list[0]) {
  503. case BOOT_DEVICE_SPI:
  504. spl_boot_list[1] = BOOT_DEVICE_UART;
  505. break;
  506. case BOOT_DEVICE_MMC1:
  507. spl_boot_list[1] = BOOT_DEVICE_SPI;
  508. spl_boot_list[2] = BOOT_DEVICE_UART;
  509. break;
  510. default:
  511. printf("Boot device %x\n", spl_boot_list[0]);
  512. }
  513. }
  514. /*
  515. * This is used because get_ram_size() does not
  516. * take care of cache, resulting a wrong size
  517. * pfla02 has just 1, 2 or 4 GB option
  518. * Function checks for mirrors in the first CS
  519. */
  520. #define RAM_TEST_PATTERN 0xaa5555aa
  521. #define MIN_BANK_SIZE (512 * 1024 * 1024)
  522. static unsigned int pfla02_detect_chiptype(void)
  523. {
  524. u32 *p, *p1;
  525. unsigned int offset = MIN_BANK_SIZE;
  526. int i;
  527. for (i = 0; i < 2; i++) {
  528. p = (u32 *)PHYS_SDRAM;
  529. p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset);
  530. *p1 = 0;
  531. *p = RAM_TEST_PATTERN;
  532. /*
  533. * This is required to detect mirroring
  534. * else we read back values from cache
  535. */
  536. flush_dcache_all();
  537. if (*p == *p1)
  538. return i;
  539. }
  540. return RAM_MT256K;
  541. }
  542. void board_init_f(ulong dummy)
  543. {
  544. unsigned int ramchip;
  545. struct mx6_ddr_sysinfo sysinfo = {
  546. /* width of data bus:0=16,1=32,2=64 */
  547. .dsize = 2,
  548. /* config for full 4GB range so that get_mem_size() works */
  549. .cs_density = 32, /* 512 MB */
  550. /* single chip select */
  551. #if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
  552. .ncs = 1,
  553. #else
  554. .ncs = 2,
  555. #endif
  556. .cs1_mirror = 1,
  557. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  558. .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
  559. .walat = 1, /* Write additional latency */
  560. .ralat = 5, /* Read additional latency */
  561. .mif3_mode = 3, /* Command prediction working mode */
  562. .bi_on = 1, /* Bank interleaving enabled */
  563. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  564. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  565. .ddr_type = DDR_TYPE_DDR3,
  566. .refsel = 1, /* Refresh cycles at 32KHz */
  567. .refr = 7, /* 8 refresh commands per refresh cycle */
  568. };
  569. #if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
  570. /* Enable NAND */
  571. setup_gpmi_nand();
  572. #endif
  573. /* setup clock gating */
  574. ccgr_init();
  575. /* setup AIPS and disable watchdog */
  576. arch_cpu_init();
  577. /* setup AXI */
  578. gpr_init();
  579. board_early_init_f();
  580. /* setup GP timer */
  581. timer_init();
  582. /* UART clocks enabled and gd valid - init serial console */
  583. preloader_console_init();
  584. setup_spi();
  585. setup_gpios();
  586. /* DDR initialization */
  587. spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
  588. ramchip = pfla02_detect_chiptype();
  589. debug("Detected chip %d\n", ramchip);
  590. #if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
  591. switch (ramchip) {
  592. case RAM_MT64K:
  593. sysinfo.cs_density = 6;
  594. break;
  595. case RAM_MT128K:
  596. sysinfo.cs_density = 10;
  597. break;
  598. case RAM_MT256K:
  599. sysinfo.cs_density = 18;
  600. break;
  601. }
  602. #endif
  603. spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
  604. /* Clear the BSS. */
  605. memset(__bss_start, 0, __bss_end - __bss_start);
  606. phyflex_err006282_workaround();
  607. /* load/boot image from boot device */
  608. board_init_r(NULL, 0);
  609. }
  610. #endif