as3722_init.c 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <asm/arch-tegra/tegra_i2c.h>
  10. #include <linux/delay.h>
  11. #include "as3722_init.h"
  12. /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
  13. void tegra_i2c_ll_write_addr(uint addr, uint config)
  14. {
  15. struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  16. writel(addr, &reg->cmd_addr0);
  17. writel(config, &reg->cnfg);
  18. }
  19. void tegra_i2c_ll_write_data(uint data, uint config)
  20. {
  21. struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  22. writel(data, &reg->cmd_data1);
  23. writel(config, &reg->cnfg);
  24. }
  25. void pmic_enable_cpu_vdd(void)
  26. {
  27. debug("%s entry\n", __func__);
  28. #ifdef AS3722_SD1VOLTAGE_DATA
  29. /* Set up VDD_CORE, for boards where OTP is incorrect*/
  30. debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
  31. /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
  32. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  33. tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
  34. /*
  35. * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  36. * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
  37. */
  38. udelay(10 * 1000);
  39. #endif
  40. debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
  41. /*
  42. * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
  43. * First set VDD to 1.0V, then enable the VDD regulator.
  44. */
  45. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  46. tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
  47. /*
  48. * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  49. * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
  50. */
  51. udelay(10 * 1000);
  52. debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
  53. /*
  54. * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
  55. * First set VDD to 1.0V, then enable the VDD regulator.
  56. */
  57. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  58. tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  59. /*
  60. * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  61. * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
  62. */
  63. udelay(10 * 1000);
  64. debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
  65. /*
  66. * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
  67. * First set VDD to 1.2V, then enable the VDD regulator.
  68. */
  69. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  70. tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
  71. /*
  72. * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  73. * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
  74. */
  75. udelay(10 * 1000);
  76. debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
  77. /*
  78. * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
  79. * First set it to bypass 3.3V straight thru, then enable the regulator
  80. *
  81. * NOTE: We do this early because doing it later seems to hose the CPU
  82. * power rail/partition startup. Need to debug.
  83. */
  84. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  85. tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  86. /*
  87. * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  88. * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
  89. */
  90. udelay(10 * 1000);
  91. }