nyan-big.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <log.h>
  10. #include <asm/gpio.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/pinmux.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/mc.h>
  15. #include <asm/arch-tegra/clk_rst.h>
  16. #include <asm/arch-tegra/pmc.h>
  17. #include <linux/delay.h>
  18. #include <power/as3722.h>
  19. #include <power/pmic.h>
  20. #include "pinmux-config-nyan-big.h"
  21. /*
  22. * Routine: pinmux_init
  23. * Description: Do individual peripheral pinmux configs
  24. */
  25. void pinmux_init(void)
  26. {
  27. gpio_config_table(nyan_big_gpio_inits,
  28. ARRAY_SIZE(nyan_big_gpio_inits));
  29. pinmux_config_pingrp_table(nyan_big_pingrps,
  30. ARRAY_SIZE(nyan_big_pingrps));
  31. pinmux_config_drvgrp_table(nyan_big_drvgrps,
  32. ARRAY_SIZE(nyan_big_drvgrps));
  33. }
  34. int tegra_board_id(void)
  35. {
  36. static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
  37. TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
  38. -1};
  39. gpio_claim_vector(vector, "board_id%d");
  40. return gpio_get_values_as_int(vector);
  41. }
  42. int tegra_lcd_pmic_init(int board_id)
  43. {
  44. struct udevice *dev;
  45. int ret;
  46. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  47. DM_GET_DRIVER(pmic_as3722), &dev);
  48. if (ret) {
  49. debug("%s: Failed to find PMIC\n", __func__);
  50. return ret;
  51. }
  52. if (board_id == 0)
  53. pmic_reg_write(dev, 0x00, 0x3c);
  54. else
  55. pmic_reg_write(dev, 0x00, 0x50);
  56. pmic_reg_write(dev, 0x12, 0x10);
  57. pmic_reg_write(dev, 0x0c, 0x07);
  58. pmic_reg_write(dev, 0x20, 0x10);
  59. return 0;
  60. }
  61. /* Setup required information for Linux kernel */
  62. static void setup_kernel_info(void)
  63. {
  64. struct mc_ctlr *mc = (void *)NV_PA_MC_BASE;
  65. /* The kernel graphics driver needs this region locked down */
  66. writel(0, &mc->mc_video_protect_bom);
  67. writel(0, &mc->mc_video_protect_size_mb);
  68. writel(1, &mc->mc_video_protect_reg_ctrl);
  69. }
  70. /*
  71. * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
  72. * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
  73. * Otherwise reading AHUB devices will hang when the kernel boots.
  74. */
  75. static void enable_required_clocks(void)
  76. {
  77. static enum periph_id ids[] = {
  78. PERIPH_ID_I2S0,
  79. PERIPH_ID_I2S1,
  80. PERIPH_ID_I2S2,
  81. PERIPH_ID_I2S3,
  82. PERIPH_ID_I2S4,
  83. PERIPH_ID_AUDIO,
  84. PERIPH_ID_APBIF,
  85. PERIPH_ID_DAM0,
  86. PERIPH_ID_DAM1,
  87. PERIPH_ID_DAM2,
  88. PERIPH_ID_AMX0,
  89. PERIPH_ID_AMX1,
  90. PERIPH_ID_ADX0,
  91. PERIPH_ID_ADX1,
  92. PERIPH_ID_SPDIF,
  93. PERIPH_ID_AFC0,
  94. PERIPH_ID_AFC1,
  95. PERIPH_ID_AFC2,
  96. PERIPH_ID_AFC3,
  97. PERIPH_ID_AFC4,
  98. PERIPH_ID_AFC5,
  99. PERIPH_ID_EXTPERIPH1
  100. };
  101. int i;
  102. for (i = 0; i < ARRAY_SIZE(ids); i++)
  103. clock_enable(ids[i]);
  104. udelay(2);
  105. for (i = 0; i < ARRAY_SIZE(ids); i++)
  106. reset_set_enable(ids[i], 0);
  107. }
  108. int nvidia_board_init(void)
  109. {
  110. clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000);
  111. clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000);
  112. /* For external MAX98090 audio codec */
  113. clock_external_output(1);
  114. setup_kernel_info();
  115. enable_required_clocks();
  116. return 0;
  117. }