jr2.c 3.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2018 Microsemi Corporation
  4. */
  5. #include <common.h>
  6. #include <image.h>
  7. #include <init.h>
  8. #include <asm/io.h>
  9. #include <led.h>
  10. #include <miiphy.h>
  11. #include <linux/bitops.h>
  12. #include <linux/delay.h>
  13. enum {
  14. BOARD_TYPE_PCB110 = 0xAABBCE00,
  15. BOARD_TYPE_PCB111,
  16. BOARD_TYPE_PCB112,
  17. };
  18. int board_early_init_r(void)
  19. {
  20. /* Prepare SPI controller to be used in master mode */
  21. writel(0, BASE_CFG + ICPU_SW_MODE);
  22. clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  23. ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
  24. ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
  25. /* Address of boot parameters */
  26. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
  27. /* LED setup */
  28. if (IS_ENABLED(CONFIG_LED))
  29. led_default_state();
  30. return 0;
  31. }
  32. static void vcoreiii_gpio_set_alternate(int gpio, int mode)
  33. {
  34. u32 mask;
  35. u32 val0, val1;
  36. void __iomem *reg0, *reg1;
  37. if (gpio < 32) {
  38. mask = BIT(gpio);
  39. reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0);
  40. reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1);
  41. } else {
  42. gpio -= 32;
  43. mask = BIT(gpio);
  44. reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0);
  45. reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1);
  46. }
  47. val0 = readl(reg0);
  48. val1 = readl(reg1);
  49. if (mode == 1) {
  50. writel(val0 | mask, reg0);
  51. writel(val1 & ~mask, reg1);
  52. } else if (mode == 2) {
  53. writel(val0 & ~mask, reg0);
  54. writel(val1 | mask, reg1);
  55. } else if (mode == 3) {
  56. writel(val0 | mask, reg0);
  57. writel(val1 | mask, reg1);
  58. } else {
  59. writel(val0 & ~mask, reg0);
  60. writel(val1 & ~mask, reg1);
  61. }
  62. }
  63. int board_phy_config(struct phy_device *phydev)
  64. {
  65. if (gd->board_type == BOARD_TYPE_PCB110 ||
  66. gd->board_type == BOARD_TYPE_PCB112) {
  67. phy_write(phydev, 0, 31, 0x10);
  68. phy_write(phydev, 0, 18, 0x80F0);
  69. while (phy_read(phydev, 0, 18) & 0x8000)
  70. ;
  71. phy_write(phydev, 0, 31, 0);
  72. }
  73. if (gd->board_type == BOARD_TYPE_PCB111) {
  74. phy_write(phydev, 0, 31, 0x10);
  75. phy_write(phydev, 0, 18, 0x80A0);
  76. while (phy_read(phydev, 0, 18) & 0x8000)
  77. ;
  78. phy_write(phydev, 0, 14, 0x800);
  79. phy_write(phydev, 0, 31, 0);
  80. }
  81. return 0;
  82. }
  83. void board_debug_uart_init(void)
  84. {
  85. /* too early for the pinctrl driver, so configure the UART pins here */
  86. vcoreiii_gpio_set_alternate(10, 1);
  87. vcoreiii_gpio_set_alternate(11, 1);
  88. }
  89. static void do_board_detect(void)
  90. {
  91. int i;
  92. u16 pval;
  93. /* MIIM 1 + 2 MDC/MDIO */
  94. for (i = 56; i < 60; i++)
  95. vcoreiii_gpio_set_alternate(i, 1);
  96. /* small delay for settling the pins */
  97. mdelay(30);
  98. if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
  99. ((pval >> 4) & 0x3F) == 0x3c) {
  100. gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
  101. } else if (mscc_phy_rd(1, 0x0, 0x3, &pval) == 0 &&
  102. ((pval >> 4) & 0x3F) == 0x3c) {
  103. gd->board_type = BOARD_TYPE_PCB110; /* Jr2-24 */
  104. } else {
  105. /* Fall-back */
  106. gd->board_type = BOARD_TYPE_PCB111; /* Jr2-48 */
  107. }
  108. }
  109. #if defined(CONFIG_MULTI_DTB_FIT)
  110. int board_fit_config_name_match(const char *name)
  111. {
  112. if (gd->board_type == BOARD_TYPE_PCB110 &&
  113. strcmp(name, "jr2_pcb110") == 0)
  114. return 0;
  115. if (gd->board_type == BOARD_TYPE_PCB111 &&
  116. strcmp(name, "jr2_pcb111") == 0)
  117. return 0;
  118. if (gd->board_type == BOARD_TYPE_PCB112 &&
  119. strcmp(name, "serval2_pcb112") == 0)
  120. return 0;
  121. return -1;
  122. }
  123. #endif
  124. #if defined(CONFIG_DTB_RESELECT)
  125. int embedded_dtb_select(void)
  126. {
  127. do_board_detect();
  128. fdtdec_setup();
  129. return 0;
  130. }
  131. #endif