helios4.c 3.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
  4. * based on board/solidrun/clearfog/clearfog.c
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <init.h>
  9. #include <miiphy.h>
  10. #include <net.h>
  11. #include <netdev.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/soc.h>
  15. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  16. #include <../serdes/a38x/high_speed_env_spec.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /*
  19. * Those values and defines are taken from the Marvell U-Boot version
  20. * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog
  21. */
  22. #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
  23. #define BOARD_GPP_OUT_ENA_MID 0xffffffff
  24. #define BOARD_GPP_OUT_VAL_LOW 0x0
  25. #define BOARD_GPP_OUT_VAL_MID 0x0
  26. #define BOARD_GPP_POL_LOW 0x0
  27. #define BOARD_GPP_POL_MID 0x0
  28. static struct serdes_map board_serdes_map[] = {
  29. {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  30. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  31. {SATA1, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  32. {SATA3, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  33. {SATA2, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  34. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  35. };
  36. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  37. {
  38. *serdes_map_array = board_serdes_map;
  39. *count = ARRAY_SIZE(board_serdes_map);
  40. return 0;
  41. }
  42. /*
  43. * Define the DDR layout / topology here in the board file. This will
  44. * be used by the DDR3 init code in the SPL U-Boot version to configure
  45. * the DDR3 controller.
  46. */
  47. static struct mv_ddr_topology_map board_topology_map = {
  48. DEBUG_LEVEL_ERROR,
  49. 0x1, /* active interfaces */
  50. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  51. { { { {0x1, 0, 0, 0},
  52. {0x1, 0, 0, 0},
  53. {0x1, 0, 0, 0},
  54. {0x1, 0, 0, 0},
  55. {0x1, 0, 0, 0} },
  56. SPEED_BIN_DDR_1600K, /* speed_bin */
  57. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  58. MV_DDR_DIE_CAP_8GBIT, /* mem_size */
  59. MV_DDR_FREQ_800, /* frequency */
  60. 0, 0, /* cas_wl cas_l */
  61. MV_DDR_TEMP_LOW, /* temperature */
  62. MV_DDR_TIM_DEFAULT} }, /* timing */
  63. BUS_MASK_32BIT_ECC, /* Busses mask */
  64. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  65. { {0} }, /* raw spd data */
  66. {0} /* timing parameters */
  67. };
  68. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  69. {
  70. /* Return the board topology as defined in the board code */
  71. return &board_topology_map;
  72. }
  73. int board_early_init_f(void)
  74. {
  75. /* Configure MPP */
  76. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  77. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  78. writel(0x10400011, MVEBU_MPP_BASE + 0x08);
  79. writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
  80. writel(0x44400002, MVEBU_MPP_BASE + 0x10);
  81. writel(0x41144004, MVEBU_MPP_BASE + 0x14);
  82. writel(0x40333333, MVEBU_MPP_BASE + 0x18);
  83. writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  84. /* Set GPP Out value */
  85. writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  86. writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  87. /* Set GPP Polarity */
  88. writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  89. writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  90. /* Set GPP Out Enable */
  91. writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  92. writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  93. return 0;
  94. }
  95. int board_init(void)
  96. {
  97. /* Address of boot parameters */
  98. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  99. return 0;
  100. }
  101. int checkboard(void)
  102. {
  103. puts("Board: Helios4\n");
  104. return 0;
  105. }
  106. int board_eth_init(struct bd_info *bis)
  107. {
  108. cpu_eth_init(bis); /* Built in controller(s) come first */
  109. return pci_eth_init(bis);
  110. }