pci.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Keymile AG
  4. * Valentin Longchamp <valentin.longchamp@keymile.com>
  5. *
  6. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <init.h>
  11. #include <pci.h>
  12. #include <asm/fsl_pci.h>
  13. #include <linux/delay.h>
  14. #include <linux/libfdt.h>
  15. #include <fdt_support.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <linux/errno.h>
  18. #include "../common/qrio.h"
  19. #include "kmp204x.h"
  20. #define PROM_SEL_L 11
  21. /* control the PROM_SEL_L signal*/
  22. static void toggle_fpga_eeprom_bus(bool cpu_own)
  23. {
  24. qrio_gpio_direction_output(QRIO_GPIO_A, PROM_SEL_L, !cpu_own);
  25. }
  26. #define CONF_SEL_L 10
  27. #define FPGA_PROG_L 19
  28. #define FPGA_DONE 18
  29. #define FPGA_INIT_L 17
  30. int trigger_fpga_config(void)
  31. {
  32. int ret = 0, init_l;
  33. /* approx 10ms */
  34. u32 timeout = 10000;
  35. /* make sure the FPGA_can access the EEPROM */
  36. toggle_fpga_eeprom_bus(false);
  37. /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
  38. qrio_gpio_direction_output(QRIO_GPIO_A, CONF_SEL_L, 0);
  39. /* trigger the config start */
  40. qrio_gpio_direction_output(QRIO_GPIO_A, FPGA_PROG_L, 0);
  41. /* small delay for INIT_L line */
  42. udelay(10);
  43. /* wait for FPGA_INIT to be asserted */
  44. do {
  45. init_l = qrio_get_gpio(QRIO_GPIO_A, FPGA_INIT_L);
  46. if (timeout-- == 0) {
  47. printf("FPGA_INIT timeout\n");
  48. ret = -EFAULT;
  49. break;
  50. }
  51. udelay(10);
  52. } while (init_l);
  53. /* deassert FPGA_PROG, config should start */
  54. qrio_set_gpio(QRIO_GPIO_A, FPGA_PROG_L, 1);
  55. return ret;
  56. }
  57. /* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
  58. static int wait_for_fpga_config(void)
  59. {
  60. int ret = 0, done;
  61. /* approx 5 s */
  62. u32 timeout = 500000;
  63. printf("PCIe FPGA config:");
  64. do {
  65. done = qrio_get_gpio(QRIO_GPIO_A, FPGA_DONE);
  66. if (timeout-- == 0) {
  67. printf(" FPGA_DONE timeout\n");
  68. ret = -EFAULT;
  69. goto err_out;
  70. }
  71. udelay(10);
  72. } while (!done);
  73. printf(" done\n");
  74. err_out:
  75. /* deactive CONF_SEL and give the CPU conf EEPROM access */
  76. qrio_set_gpio(QRIO_GPIO_A, CONF_SEL_L, 1);
  77. toggle_fpga_eeprom_bus(true);
  78. return ret;
  79. }
  80. #define PCIE_SW_RST 14
  81. #define PEXHC_RST 13
  82. #define HOOPER_RST 12
  83. void pci_init_board(void)
  84. {
  85. qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  86. qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  87. qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  88. /* wait for the PCIe FPGA to be configured
  89. * it has been triggered earlier in board_early_init_r */
  90. if (wait_for_fpga_config())
  91. printf("error finishing PCIe FPGA config\n");
  92. qrio_prst(PCIE_SW_RST, false, false);
  93. qrio_prst(PEXHC_RST, false, false);
  94. qrio_prst(HOOPER_RST, false, false);
  95. /* Hooper is not direcly PCIe capable */
  96. mdelay(50);
  97. fsl_pcie_init_board(0);
  98. }
  99. void pci_of_setup(void *blob, struct bd_info *bd)
  100. {
  101. FT_FSL_PCI_SETUP;
  102. }