kwbimage_128M16_1.cfg 9.0 KB

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  1. # SPDX-License-Identifier: GPL-2.0+
  2. #
  3. # (C) Copyright 2010
  4. # Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. #
  6. # (C) Copyright 2012
  7. # Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
  8. # Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
  9. #
  10. # (C) Copyright 2012
  11. #
  12. # Refer doc/README.kwbimage for more details about how-to configure
  13. # and create kirkwood boot image
  14. #
  15. # Boot Media configurations
  16. BOOT_FROM spi # Boot from SPI flash
  17. DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
  18. # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
  19. # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
  20. # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
  21. # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
  22. # bit 19-16: 1, MPPSel4 NF_IO[6]
  23. # bit 23-20: 1, MPPSel5 NF_IO[7]
  24. # bit 27-24: 1, MPPSel6 SYSRST_O
  25. # bit 31-28: 0, MPPSel7 GPO[7]
  26. DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
  27. # bit 3-0: 0, MPPSel8 GPIO[8]
  28. # bit 7-4: 0, MPPSel9 GPIO[9]
  29. # bit 12-8: 3, MPPSel10 UA0_TXD
  30. # bit 15-12: 3, MPPSel11 UA0_RXD
  31. # bit 19-16: 0, MPPSel12 not connected
  32. # bit 23-20: 3, MPPSel13 UA1_TXD
  33. # bit 27-24: 3, MPPSel14 UA1_RXD
  34. # bit 31-28: 0, MPPSel15 GPIO[15]
  35. DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
  36. # bit 3-0: 0, MPPSel16 GPIO[16]
  37. # bit 7-4: 0, MPPSel17 not connected
  38. # bit 12-8: 1, MPPSel18 NF_IO[0]
  39. # bit 15-12: 1, MPPSel19 NF_IO[1]
  40. # bit 19-16: 0, MPPSel20 GPIO[20]
  41. # bit 23-20: 0, MPPSel21 GPIO[21]
  42. # bit 27-24: 0, MPPSel22 GPIO[22]
  43. # bit 31-28: 0, MPPSel23 GPIO[23]
  44. # MPP Control 3-6 Register untouched (MPP24-49)
  45. DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
  46. # bit 2-0: 3, Reserved
  47. # bit 5-3: 3, Reserved
  48. # bit 6: 0, Reserved
  49. # bit 7: 0, RGMII-pads voltage = 3.3V
  50. # bit 10-8: 3, Reserved
  51. # bit 13-11: 3, Reserved
  52. # bit 14: 0, Reserved
  53. # bit 15: 0, MPP RGMII-pads voltage = 3.3V
  54. # bit 31-16 0x1B1B, Reserved
  55. DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
  56. # bit 0-1: 2, Tag RAM RTC RAM0
  57. # bit 3-2: 1, Tag RAM WTC RAM0
  58. # bit 7-4: 6, Reserve
  59. # bit 9-8: 2, Valid RAM RTC RAM
  60. # bit 11-10: 1, Valid RAM WTC RAM
  61. # bit 13-12: 2, Dirty RAM RTC RAM
  62. # bit 15-14: 1, Dirty RAM WTC RAM
  63. # bit 17-16: 2, Data RAM RTC RAM0
  64. # bit 19-18: 1, Data RAM WTC RAM0
  65. # bit 21-20: 2, Data RAM RTC RAM1
  66. # bit 23-22: 1, Data RAM WTC RAM1
  67. # bit 25-24: 2, Data RAM RTC RAM2
  68. # bit 27-26: 1, Data RAM WTC RAM2
  69. # bit 29-28: 2, Data RAM RTC RAM3
  70. # bit 31-30: 1, Data RAM WTC RAM4
  71. DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
  72. # bit 15-0: ???, Reserve
  73. # bit 17-16: 2, ECC RAM RTC RAM0
  74. # bit 19-18: 1, ECC RAM WTC RAM0
  75. # bit 31-20: ???,Reserve
  76. # NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
  77. # If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
  78. # SDRAM initalization
  79. DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
  80. # bit 13-0: 0x4E0, DDR2 clks refresh rate
  81. # bit 14: 0, reserved
  82. # bit 15: 0, reserved
  83. # bit 16: 0, CPU to Dram Write buffer policy
  84. # bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
  85. # bit 19-18: 0, reserved
  86. # bit 23-20: 0, reserved
  87. # bit 24: 1, enable exit self refresh mode on DDR access
  88. # bit 25: 1, required
  89. # bit 29-26: 0, reserved
  90. # bit 31-30: 1, reserved
  91. DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
  92. # bit 3-0: 0, reserved
  93. # bit 4: 0, 2T mode =addr/cmd in same cycle
  94. # bit 5: 0, clk is driven during self refresh, we don't care for APX
  95. # bit 6: 0, use recommended falling edge of clk for addr/cmd
  96. # bit 7-11: 0, reserved
  97. # bit 12-13: 1, reserved, required 1
  98. # bit 14: 0, input buffer always powered up
  99. # bit 17-15: 0, reserved
  100. # bit 18: 1, cpu lock transaction enabled
  101. # bit 19: 0, reserved
  102. # bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
  103. # bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
  104. # bit 30-28: 3, required
  105. # bit 31: 0,no additional STARTBURST delay
  106. DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
  107. # bit 3-0: 0xE, TRAS, 15 clk (45 ns)
  108. # bit 7-4: 0x4, TRCD, 5 clk (15 ns)
  109. # bit 11-8: 0x4, TRP, 5 clk (15 ns)
  110. # bit 15-12: 0x4, TWR, 5 clk (15 ns)
  111. # bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
  112. # bit 20: 0, extended TRAS msb
  113. # bit 23-21: 0, reserved
  114. # bit 27-24: 0x3, TRRD, 4 clk (10 ns)
  115. # bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
  116. DATA 0xFFD0140C 0x0000003e # DDR Timing (High)
  117. # bit 6-0: 0x3E, TRFC, 63 clk (195 ns)
  118. # bit 8-7: 0, TR2R
  119. # bit 10-9: 0, TR2W
  120. # bit 12-11: 0, TW2W
  121. # bit 31-13: 0, reserved
  122. DATA 0xFFD01410 0x00000001 # DDR Address Control
  123. # bit 1-0: 1, Cs0width=x16
  124. # bit 3-2: 0, Cs0size=2Gb
  125. # bit 5-4: 0, Cs1width=nonexistent
  126. # bit 7-6: 0, Cs1size =nonexistent
  127. # bit 9-8: 0, Cs2width=nonexistent
  128. # bit 11-10: 0, Cs2size =nonexistent
  129. # bit 13-12: 0, Cs3width=nonexistent
  130. # bit 15-14: 0, Cs3size =nonexistent
  131. # bit 16: 0, Cs0AddrSel
  132. # bit 17: 0, Cs1AddrSel
  133. # bit 18: 0, Cs2AddrSel
  134. # bit 19: 0, Cs3AddrSel
  135. # bit 31-20: 0, required
  136. DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
  137. # bit 0: 0, OpenPage enabled
  138. # bit 31-1: 0, required
  139. DATA 0xFFD01418 0x00000000 # DDR Operation
  140. # bit 3-0: 0, DDR cmd
  141. # bit 31-4: 0, required
  142. DATA 0xFFD0141C 0x00000652 # DDR Mode
  143. # bit 2-0: 2, Burst Length = 4
  144. # bit 3: 0, Burst Type
  145. # bit 6-4: 5, CAS Latency = 5
  146. # bit 7: 0, Test mode
  147. # bit 8: 0, DLL Reset
  148. # bit 11-9: 3, Write recovery for auto-precharge must be 3
  149. # bit 12: 0, Active power down exit time, fast exit
  150. # bit 14-13: 0, reserved
  151. # bit 31-15: 0, reserved
  152. DATA 0xFFD01420 0x00000006 # DDR Extended Mode
  153. # bit 0: 0, DDR DLL enabled
  154. # bit 1: 1, DDR drive strength reduced
  155. # bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0]
  156. # bit 5-3: 0, required
  157. # bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1]
  158. # bit 9-7: 0, required
  159. # bit 10: 0, differential DQS enabled
  160. # bit 11: 0, required
  161. # bit 12: 0, DDR output buffer enabled
  162. # bit 31-13: 0 required
  163. DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
  164. # bit 2-0: 7, required
  165. # bit 3: 1, MBUS Burst Chop disabled
  166. # bit 6-4: 7, required
  167. # bit 7: 0, reserved
  168. # bit 8: 1, add sample stage required for f > 266 MHz
  169. # bit 9: 0, no half clock cycle addition to dataout
  170. # bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
  171. # bit 11: 0, 1/4 clock cycle skew disabled for write mesh
  172. # bit 15-12:0xf, required
  173. # bit 31-16: 0, required
  174. DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
  175. # bit 3-0: 0, required
  176. # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
  177. # bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
  178. # (ODT turn off delay 2,5 clk cycles)
  179. # bit 15-12: 4, internal ODT time based on bit 7-4
  180. # with the considered SDRAM internal delay
  181. # bit 19-16: 8, internal ODT de-assertion based on bit 11-8
  182. # with the considered SDRAM internal delay
  183. # bit 31-20: 0, required
  184. DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
  185. # bit 3-0: 2, M_ODT assertion same as bit 11-8
  186. # bit 7-4: 5, M_ODT de-assertion same as bit 15-12
  187. # bit 11-8: 4, internal ODT assertion 2 cycles after write start command
  188. # with the considered SDRAM internal delay
  189. # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
  190. # with the considered SDRAM internal delay
  191. DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
  192. # bit 23-0: 0, reserved
  193. # bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
  194. DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
  195. # bit 0: 1, Window enabled
  196. # bit 1: 0, Write Protect disabled
  197. # bit 3-2: 0, CS0 hit selected
  198. # bit 23-4:ones, required
  199. # bit 31-24: 0x0F, Size (i.e. 256MB)
  200. DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
  201. DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
  202. DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
  203. DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
  204. # bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
  205. # bit 7-4: 0, ODT0Rd, MODT[1] not asserted
  206. # bit 11-8: 0, required
  207. # big 15-11: 0, required
  208. # bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
  209. # bit 23-20: 0, ODT0Wr, MODT[1] not asserted
  210. # bit 27-24: 0, required
  211. # bit 31-28: 0, required
  212. DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
  213. # bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
  214. # bit 3-2: 0, ODT1 controlled by register
  215. # bit 31-4: 0, required
  216. DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
  217. # bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0
  218. # bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM
  219. # bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr
  220. # bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
  221. # bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
  222. # bit 14: 1, STARTBURST ODT enabled
  223. # bit 15: 1, Use ODT Block
  224. DATA 0xFFD01480 0x00000001 # DDR Initialization Control
  225. # bit 0: 1, enable DDR init upon this register write
  226. # bit 31-1: 0, reserved
  227. # End of Header extension
  228. DATA 0x0 0x0