km_arm.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Prafulla Wadaskar <prafulla@marvell.com>
  6. *
  7. * (C) Copyright 2009
  8. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  9. *
  10. * (C) Copyright 2010
  11. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  12. */
  13. #include <common.h>
  14. #include <env.h>
  15. #include <i2c.h>
  16. #include <init.h>
  17. #include <nand.h>
  18. #include <net.h>
  19. #include <netdev.h>
  20. #include <miiphy.h>
  21. #include <spi.h>
  22. #include <asm/io.h>
  23. #include <asm/arch/cpu.h>
  24. #include <asm/arch/soc.h>
  25. #include <asm/arch/mpp.h>
  26. #include "../common/common.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /*
  29. * BOCO FPGA definitions
  30. */
  31. #define BOCO 0x10
  32. #define REG_CTRL_H 0x02
  33. #define MASK_WRL_UNITRUN 0x01
  34. #define MASK_RBX_PGY_PRESENT 0x40
  35. #define REG_IRQ_CIRQ2 0x2d
  36. #define MASK_RBI_DEFECT_16 0x01
  37. /*
  38. * PHY registers definitions
  39. */
  40. #define PHY_MARVELL_OUI 0x5043
  41. #define PHY_MARVELL_88E1118_MODEL 0x0022
  42. #define PHY_MARVELL_88E1118R_MODEL 0x0024
  43. #define PHY_MARVELL_PAGE_REG 0x0016
  44. #define PHY_MARVELL_DEFAULT_PAGE 0x0000
  45. #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
  46. #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
  47. #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
  48. #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
  49. #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
  50. #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
  51. /* I/O pin to erase flash RGPP09 = MPP43 */
  52. #define KM_FLASH_ERASE_ENABLE 43
  53. /* Multi-Purpose Pins Functionality configuration */
  54. static const u32 kwmpp_config[] = {
  55. MPP0_NF_IO2,
  56. MPP1_NF_IO3,
  57. MPP2_NF_IO4,
  58. MPP3_NF_IO5,
  59. MPP4_NF_IO6,
  60. MPP5_NF_IO7,
  61. MPP6_SYSRST_OUTn,
  62. MPP7_PEX_RST_OUTn,
  63. #if defined(CONFIG_SYS_I2C_SOFT)
  64. MPP8_GPIO, /* SDA */
  65. MPP9_GPIO, /* SCL */
  66. #endif
  67. MPP10_UART0_TXD,
  68. MPP11_UART0_RXD,
  69. MPP12_GPO, /* Reserved */
  70. MPP13_UART1_TXD,
  71. MPP14_UART1_RXD,
  72. MPP15_GPIO, /* Not used */
  73. MPP16_GPIO, /* Not used */
  74. MPP17_GPIO, /* Reserved */
  75. MPP18_NF_IO0,
  76. MPP19_NF_IO1,
  77. MPP20_GPIO,
  78. MPP21_GPIO,
  79. MPP22_GPIO,
  80. MPP23_GPIO,
  81. MPP24_GPIO,
  82. MPP25_GPIO,
  83. MPP26_GPIO,
  84. MPP27_GPIO,
  85. MPP28_GPIO,
  86. MPP29_GPIO,
  87. MPP30_GPIO,
  88. MPP31_GPIO,
  89. MPP32_GPIO,
  90. MPP33_GPIO,
  91. MPP34_GPIO, /* CDL1 (input) */
  92. MPP35_GPIO, /* CDL2 (input) */
  93. MPP36_GPIO, /* MAIN_IRQ (input) */
  94. MPP37_GPIO, /* BOARD_LED */
  95. MPP38_GPIO, /* Piggy3 LED[1] */
  96. MPP39_GPIO, /* Piggy3 LED[2] */
  97. MPP40_GPIO, /* Piggy3 LED[3] */
  98. MPP41_GPIO, /* Piggy3 LED[4] */
  99. MPP42_GPIO, /* Piggy3 LED[5] */
  100. MPP43_GPIO, /* Piggy3 LED[6] */
  101. MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
  102. MPP45_GPIO, /* Piggy3 LED[8] */
  103. MPP46_GPIO, /* Reserved */
  104. MPP47_GPIO, /* Reserved */
  105. MPP48_GPIO, /* Reserved */
  106. MPP49_GPIO, /* SW_INTOUTn */
  107. 0
  108. };
  109. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  110. #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
  111. /*
  112. * All boards with PIGGY4 connected via a simple switch have ethernet always
  113. * present.
  114. */
  115. int ethernet_present(void)
  116. {
  117. return 1;
  118. }
  119. #else
  120. int ethernet_present(void)
  121. {
  122. uchar buf;
  123. int ret = 0;
  124. if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
  125. printf("%s: Error reading Boco\n", __func__);
  126. return -1;
  127. }
  128. if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
  129. ret = 1;
  130. return ret;
  131. }
  132. #endif
  133. static int initialize_unit_leds(void)
  134. {
  135. /*
  136. * Init the unit LEDs per default they all are
  137. * ok apart from bootstat
  138. */
  139. uchar buf;
  140. if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
  141. printf("%s: Error reading Boco\n", __func__);
  142. return -1;
  143. }
  144. buf |= MASK_WRL_UNITRUN;
  145. if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
  146. printf("%s: Error writing Boco\n", __func__);
  147. return -1;
  148. }
  149. return 0;
  150. }
  151. static void set_bootcount_addr(void)
  152. {
  153. uchar buf[32];
  154. unsigned int bootcountaddr;
  155. bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
  156. sprintf((char *)buf, "0x%x", bootcountaddr);
  157. env_set("bootcountaddr", (char *)buf);
  158. }
  159. int misc_init_r(void)
  160. {
  161. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
  162. CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
  163. initialize_unit_leds();
  164. set_km_env();
  165. set_bootcount_addr();
  166. return 0;
  167. }
  168. int board_early_init_f(void)
  169. {
  170. #if defined(CONFIG_SYS_I2C_SOFT)
  171. u32 tmp;
  172. /* set the 2 bitbang i2c pins as output gpios */
  173. tmp = readl(MVEBU_GPIO0_BASE + 4);
  174. writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
  175. #endif
  176. /* adjust SDRAM size for bank 0 */
  177. mvebu_sdram_size_adjust(0);
  178. kirkwood_mpp_conf(kwmpp_config, NULL);
  179. return 0;
  180. }
  181. int board_init(void)
  182. {
  183. /* address of boot parameters */
  184. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  185. /*
  186. * The KM_FLASH_GPIO_PIN switches between using a
  187. * NAND or a SPI FLASH. Set this pin on start
  188. * to NAND mode.
  189. */
  190. kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
  191. kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
  192. #if defined(CONFIG_SYS_I2C_SOFT)
  193. /*
  194. * Reinit the GPIO for I2C Bitbang driver so that the now
  195. * available gpio framework is consistent. The calls to
  196. * direction output in are not necessary, they are already done in
  197. * board_early_init_f
  198. */
  199. kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
  200. kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
  201. #endif
  202. #if defined(CONFIG_SYS_EEPROM_WREN)
  203. kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
  204. kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
  205. #endif
  206. #if defined(CONFIG_KM_FPGA_CONFIG)
  207. trigger_fpga_config();
  208. #endif
  209. return 0;
  210. }
  211. int board_late_init(void)
  212. {
  213. #if defined(CONFIG_KM_COGE5UN)
  214. u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
  215. /* if pin 1 do full erase */
  216. if (dip_switch != 0) {
  217. /* start bootloader */
  218. puts("DIP: Enabled\n");
  219. env_set("actual_bank", "0");
  220. }
  221. #endif
  222. #if defined(CONFIG_KM_FPGA_CONFIG)
  223. wait_for_fpga_config();
  224. fpga_reset();
  225. toggle_eeprom_spi_bus();
  226. #endif
  227. return 0;
  228. }
  229. static const u32 spi_mpp_config[] = {
  230. MPP1_SPI_MOSI,
  231. MPP2_SPI_SCK,
  232. MPP3_SPI_MISO,
  233. 0
  234. };
  235. static u32 spi_mpp_backup[4];
  236. int mvebu_board_spi_claim_bus(struct udevice *dev)
  237. {
  238. spi_mpp_backup[3] = 0;
  239. /* set new spi mpp config and save current one */
  240. kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
  241. kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
  242. return 0;
  243. }
  244. int mvebu_board_spi_release_bus(struct udevice *dev)
  245. {
  246. /* restore saved mpp config */
  247. kirkwood_mpp_conf(spi_mpp_backup, NULL);
  248. kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
  249. return 0;
  250. }
  251. #if (defined(CONFIG_KM_PIGGY4_88E6061))
  252. #define PHY_LED_SEL_REG 0x18
  253. #define PHY_LED0_LINK (0x5)
  254. #define PHY_LED1_ACT (0x8<<4)
  255. #define PHY_LED2_INT (0xe<<8)
  256. #define PHY_SPEC_CTRL_REG 0x1c
  257. #define PHY_RGMII_CLK_STABLE (0x1<<10)
  258. #define PHY_CLSA (0x1<<1)
  259. /* Configure and enable MV88E3018 PHY */
  260. void reset_phy(void)
  261. {
  262. char *name = "egiga0";
  263. unsigned short reg;
  264. if (miiphy_set_current_dev(name))
  265. return;
  266. /* RGMII clk transition on data stable */
  267. if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
  268. printf("Error reading PHY spec ctrl reg\n");
  269. if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
  270. reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
  271. printf("Error writing PHY spec ctrl reg\n");
  272. /* leds setup */
  273. if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
  274. PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
  275. printf("Error writing PHY LED reg\n");
  276. /* reset the phy */
  277. miiphy_reset(name, CONFIG_PHY_BASE_ADR);
  278. }
  279. #elif defined(CONFIG_KM_PIGGY4_88E6352)
  280. #include <mv88e6352.h>
  281. #if defined(CONFIG_KM_NUSA)
  282. struct mv88e_sw_reg extsw_conf[] = {
  283. /*
  284. * port 0, PIGGY4, autoneg
  285. * first the fix for the 1000Mbits Autoneg, this is from
  286. * a Marvell errata, the regs are undocumented
  287. */
  288. { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
  289. { PHY(0), PHY_STATUS, AN1000FIX },
  290. { PHY(0), PHY_PAGE, 0 },
  291. /* now the real port and phy configuration */
  292. { PORT(0), PORT_PHY, NO_SPEED_FOR },
  293. { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
  294. { PHY(0), PHY_1000_CTRL, NO_ADV },
  295. { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
  296. { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
  297. FULL_DUPLEX },
  298. /* port 1, unused */
  299. { PORT(1), PORT_CTRL, PORT_DIS },
  300. { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
  301. { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
  302. /* port 2, unused */
  303. { PORT(2), PORT_CTRL, PORT_DIS },
  304. { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
  305. { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
  306. /* port 3, unused */
  307. { PORT(3), PORT_CTRL, PORT_DIS },
  308. { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
  309. { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
  310. /* port 4, ICNEV, SerDes, SGMII */
  311. { PORT(4), PORT_STATUS, NO_PHY_DETECT },
  312. { PORT(4), PORT_PHY, SPEED_1000_FOR },
  313. { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
  314. { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
  315. { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
  316. /* port 5, CPU_RGMII */
  317. { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
  318. FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
  319. FULL_DPX_FOR | SPEED_1000_FOR },
  320. { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
  321. /* port 6, unused, this port has no phy */
  322. { PORT(6), PORT_CTRL, PORT_DIS },
  323. };
  324. #else
  325. struct mv88e_sw_reg extsw_conf[] = {};
  326. #endif
  327. void reset_phy(void)
  328. {
  329. #if defined(CONFIG_KM_MVEXTSW_ADDR)
  330. char *name = "egiga0";
  331. if (miiphy_set_current_dev(name))
  332. return;
  333. mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
  334. ARRAY_SIZE(extsw_conf));
  335. mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
  336. #endif
  337. }
  338. #else
  339. /* Configure and enable MV88E1118 PHY on the piggy*/
  340. void reset_phy(void)
  341. {
  342. unsigned int oui;
  343. unsigned char model, rev;
  344. char *name = "egiga0";
  345. if (miiphy_set_current_dev(name))
  346. return;
  347. /* reset the phy */
  348. miiphy_reset(name, CONFIG_PHY_BASE_ADR);
  349. /* get PHY model */
  350. if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
  351. return;
  352. /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
  353. if ((oui == PHY_MARVELL_OUI) &&
  354. (model == PHY_MARVELL_88E1118R_MODEL)) {
  355. /* set page register to 3 */
  356. if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
  357. PHY_MARVELL_PAGE_REG,
  358. PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
  359. printf("Error writing PHY page reg\n");
  360. /*
  361. * leds setup as printed on PCB:
  362. * LED2 (Link): 0x0 (On Link, Off No Link)
  363. * LED1 (Activity): 0x3 (On Activity, Off No Activity)
  364. * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
  365. */
  366. if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
  367. PHY_MARVELL_88E1118R_LED_CTRL_REG,
  368. PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
  369. PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
  370. PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
  371. PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
  372. printf("Error writing PHY LED reg\n");
  373. /* set page register back to 0 */
  374. if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
  375. PHY_MARVELL_PAGE_REG,
  376. PHY_MARVELL_DEFAULT_PAGE))
  377. printf("Error writing PHY page reg\n");
  378. }
  379. }
  380. #endif
  381. #if defined(CONFIG_HUSH_INIT_VAR)
  382. int hush_init_var(void)
  383. {
  384. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  385. return 0;
  386. }
  387. #endif
  388. #if defined(CONFIG_SYS_I2C_SOFT)
  389. void set_sda(int state)
  390. {
  391. I2C_ACTIVE;
  392. I2C_SDA(state);
  393. }
  394. void set_scl(int state)
  395. {
  396. I2C_SCL(state);
  397. }
  398. int get_sda(void)
  399. {
  400. I2C_TRISTATE;
  401. return I2C_READ;
  402. }
  403. int get_scl(void)
  404. {
  405. return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
  406. }
  407. #endif
  408. #if defined(CONFIG_POST)
  409. #define KM_POST_EN_L 44
  410. #define POST_WORD_OFF 8
  411. int post_hotkeys_pressed(void)
  412. {
  413. #if defined(CONFIG_KM_COGE5UN)
  414. return kw_gpio_get_value(KM_POST_EN_L);
  415. #else
  416. return !kw_gpio_get_value(KM_POST_EN_L);
  417. #endif
  418. }
  419. ulong post_word_load(void)
  420. {
  421. void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
  422. return in_le32(addr);
  423. }
  424. void post_word_store(ulong value)
  425. {
  426. void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
  427. out_le32(addr, value);
  428. }
  429. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  430. {
  431. *vstart = CONFIG_SYS_SDRAM_BASE;
  432. /* we go up to relocation plus a 1 MB margin */
  433. *size = CONFIG_SYS_TEXT_BASE - (1<<20);
  434. return 0;
  435. }
  436. #endif
  437. #if defined(CONFIG_SYS_EEPROM_WREN)
  438. int eeprom_write_enable(unsigned dev_addr, int state)
  439. {
  440. kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
  441. return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
  442. }
  443. #endif