ci20.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * CI20 setup code
  4. *
  5. * Copyright (c) 2013 Imagination Technologies
  6. * Author: Paul Burton <paul.burton@imgtec.com>
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <init.h>
  11. #include <net.h>
  12. #include <netdev.h>
  13. #include <asm/io.h>
  14. #include <asm/gpio.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include <mach/jz4780.h>
  18. #include <mach/jz4780_dram.h>
  19. #include <mach/jz4780_gpio.h>
  20. struct ci20_otp {
  21. u32 serial_number;
  22. u32 date;
  23. u8 manufacturer[2];
  24. u8 mac[6];
  25. } __packed;
  26. static void ci20_mux_mmc(void)
  27. {
  28. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  29. /* setup MSC1 pins */
  30. writel(0x30f00000, gpio_regs + GPIO_PXINTC(4));
  31. writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4));
  32. writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4));
  33. writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4));
  34. writel(0x30f00000, gpio_regs + GPIO_PXPENC(4));
  35. jz4780_clk_ungate_mmc();
  36. }
  37. #ifndef CONFIG_SPL_BUILD
  38. static void ci20_mux_eth(void)
  39. {
  40. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  41. #ifdef CONFIG_MTD_RAW_NAND
  42. /* setup pins (some already setup for NAND) */
  43. writel(0x04030000, gpio_regs + GPIO_PXINTC(0));
  44. writel(0x04030000, gpio_regs + GPIO_PXMASKC(0));
  45. writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0));
  46. writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0));
  47. writel(0x04030000, gpio_regs + GPIO_PXPENS(0));
  48. #else
  49. /* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */
  50. writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0));
  51. writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0));
  52. writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0));
  53. writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0));
  54. writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0));
  55. writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
  56. writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
  57. writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
  58. writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
  59. writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
  60. #endif
  61. }
  62. static void ci20_mux_jtag(void)
  63. {
  64. #ifdef CONFIG_JTAG
  65. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  66. /* enable JTAG */
  67. writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
  68. writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
  69. writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
  70. writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0));
  71. #endif
  72. }
  73. static void ci20_mux_nand(void)
  74. {
  75. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  76. /* setup pins */
  77. writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0));
  78. writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0));
  79. writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0));
  80. writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0));
  81. writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0));
  82. writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
  83. writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
  84. writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
  85. writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
  86. writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
  87. /* FRB0_N */
  88. jz47xx_gpio_direction_input(JZ_GPIO(0, 20));
  89. writel(20, gpio_regs + GPIO_PXPENS(0));
  90. /* disable write protect */
  91. jz47xx_gpio_direction_output(JZ_GPIO(5, 22), 1);
  92. }
  93. static void ci20_mux_uart(void)
  94. {
  95. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  96. /* UART0 */
  97. writel(0x9, gpio_regs + GPIO_PXINTC(5));
  98. writel(0x9, gpio_regs + GPIO_PXMASKC(5));
  99. writel(0x9, gpio_regs + GPIO_PXPAT1C(5));
  100. writel(0x9, gpio_regs + GPIO_PXPAT0C(5));
  101. writel(0x9, gpio_regs + GPIO_PXPENC(5));
  102. jz4780_clk_ungate_uart(0);
  103. /* UART 1 and 2 */
  104. jz4780_clk_ungate_uart(1);
  105. jz4780_clk_ungate_uart(2);
  106. #ifndef CONFIG_JTAG
  107. /* UART3 */
  108. writel(1 << 12, gpio_regs + GPIO_PXINTC(3));
  109. writel(1 << 12, gpio_regs + GPIO_PXMASKS(3));
  110. writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3));
  111. writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3));
  112. writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
  113. writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
  114. writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
  115. writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0));
  116. writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0));
  117. jz4780_clk_ungate_uart(3);
  118. #endif
  119. /* UART4 */
  120. writel(0x100400, gpio_regs + GPIO_PXINTC(2));
  121. writel(0x100400, gpio_regs + GPIO_PXMASKC(2));
  122. writel(0x100400, gpio_regs + GPIO_PXPAT1S(2));
  123. writel(0x100400, gpio_regs + GPIO_PXPAT0C(2));
  124. writel(0x100400, gpio_regs + GPIO_PXPENC(2));
  125. jz4780_clk_ungate_uart(4);
  126. }
  127. int board_early_init_f(void)
  128. {
  129. ci20_mux_jtag();
  130. ci20_mux_uart();
  131. ci20_mux_eth();
  132. ci20_mux_mmc();
  133. ci20_mux_nand();
  134. /* SYS_POWER_IND high (LED blue, VBUS off) */
  135. jz47xx_gpio_direction_output(JZ_GPIO(5, 15), 0);
  136. /* LEDs off */
  137. jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0);
  138. jz47xx_gpio_direction_output(JZ_GPIO(2, 1), 0);
  139. jz47xx_gpio_direction_output(JZ_GPIO(2, 2), 0);
  140. jz47xx_gpio_direction_output(JZ_GPIO(2, 3), 0);
  141. return 0;
  142. }
  143. int misc_init_r(void)
  144. {
  145. const u32 efuse_clk = jz4780_clk_get_efuse_clk();
  146. struct ci20_otp otp;
  147. char manufacturer[3];
  148. /* Read the board OTP data */
  149. jz4780_efuse_init(efuse_clk);
  150. jz4780_efuse_read(0x18, 16, (u8 *)&otp);
  151. /* Set MAC address */
  152. if (!is_valid_ethaddr(otp.mac)) {
  153. /* no MAC assigned, generate one from the unique chip ID */
  154. jz4780_efuse_read(0x8, 4, &otp.mac[0]);
  155. jz4780_efuse_read(0x12, 2, &otp.mac[4]);
  156. otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01;
  157. }
  158. eth_env_set_enetaddr("ethaddr", otp.mac);
  159. /* Put other board information into the environment */
  160. env_set_ulong("serial#", otp.serial_number);
  161. env_set_ulong("board_date", otp.date);
  162. manufacturer[0] = otp.manufacturer[0];
  163. manufacturer[1] = otp.manufacturer[1];
  164. manufacturer[2] = 0;
  165. env_set("board_mfr", manufacturer);
  166. return 0;
  167. }
  168. #ifdef CONFIG_DRIVER_DM9000
  169. int board_eth_init(struct bd_info *bis)
  170. {
  171. /* Enable clock */
  172. jz4780_clk_ungate_ethernet();
  173. /* Enable power (PB25) */
  174. jz47xx_gpio_direction_output(JZ_GPIO(1, 25), 1);
  175. /* Reset (PF12) */
  176. mdelay(10);
  177. jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 0);
  178. mdelay(10);
  179. jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 1);
  180. mdelay(10);
  181. return dm9000_initialize(bis);
  182. }
  183. #endif /* CONFIG_DRIVER_DM9000 */
  184. #endif
  185. static u8 ci20_revision(void)
  186. {
  187. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  188. int val;
  189. jz47xx_gpio_direction_input(JZ_GPIO(2, 18));
  190. jz47xx_gpio_direction_input(JZ_GPIO(2, 19));
  191. /* Enable pullups */
  192. writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2));
  193. /* Read PC18/19 for version */
  194. val = (!!jz47xx_gpio_get_value(JZ_GPIO(2, 18))) |
  195. ((!!jz47xx_gpio_get_value(JZ_GPIO(2, 19))) << 1);
  196. if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */
  197. return 1;
  198. if (val == 1) /* Rev 2 boards pulldown port C bit 18 giving 1 */
  199. return 2;
  200. return 0;
  201. }
  202. int dram_init(void)
  203. {
  204. gd->ram_size = sdram_size(0) + sdram_size(1);
  205. return 0;
  206. }
  207. /* U-Boot common routines */
  208. int checkboard(void)
  209. {
  210. printf("Board: Creator CI20 (rev.%d)\n", ci20_revision());
  211. return 0;
  212. }
  213. #ifdef CONFIG_SPL_BUILD
  214. #if defined(CONFIG_SPL_MMC_SUPPORT)
  215. int board_mmc_init(struct bd_info *bd)
  216. {
  217. ci20_mux_mmc();
  218. return jz_mmc_init((void __iomem *)MSC0_BASE);
  219. }
  220. #endif
  221. static const struct jz4780_ddr_config K4B2G0846Q_48_config = {
  222. .timing = {
  223. (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
  224. (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
  225. (4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) |
  226. (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
  227. (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
  228. (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
  229. (21 << DDRC_TIMING3_TRC_BIT),
  230. (31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
  231. (4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) |
  232. (8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
  233. (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
  234. (4 << DDRC_TIMING5_TWDLAT_BIT),
  235. (25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) |
  236. (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
  237. },
  238. /* PHY */
  239. /* Mode Register 0 */
  240. .mr0 = 0x420,
  241. #ifdef SDRAM_DISABLE_DLL
  242. .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
  243. #else
  244. .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
  245. #endif
  246. .ptr0 = 0x002000d4,
  247. .ptr1 = 0x02230d40,
  248. .ptr2 = 0x04013880,
  249. .dtpr0 = 0x2a8f6690,
  250. .dtpr1 = 0x00400860,
  251. .dtpr2 = 0x10042a00,
  252. .pullup = 0x0b,
  253. .pulldn = 0x0b,
  254. };
  255. static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
  256. .timing = {
  257. (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
  258. (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
  259. (4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) |
  260. (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
  261. (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
  262. (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
  263. (22 << DDRC_TIMING3_TRC_BIT),
  264. (42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
  265. (4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) |
  266. (3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
  267. (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
  268. (4 << DDRC_TIMING5_TWDLAT_BIT),
  269. (25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) |
  270. (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
  271. },
  272. /* PHY */
  273. /* Mode Register 0 */
  274. .mr0 = 0x420,
  275. #ifdef SDRAM_DISABLE_DLL
  276. .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
  277. #else
  278. .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
  279. #endif
  280. .ptr0 = 0x002000d4,
  281. .ptr1 = 0x02d30d40,
  282. .ptr2 = 0x04013880,
  283. .dtpr0 = 0x2c906690,
  284. .dtpr1 = 0x005608a0,
  285. .dtpr2 = 0x10042a00,
  286. .pullup = 0x0e,
  287. .pulldn = 0x0e,
  288. };
  289. #if (CONFIG_SYS_MHZ != 1200)
  290. #error No DDR configuration for CPU speed
  291. #endif
  292. const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
  293. {
  294. const int board_revision = ci20_revision();
  295. if (board_revision == 2)
  296. return &K4B2G0846Q_48_config;
  297. else /* Fall back to H5TQ2G83CFR RAM */
  298. return &H5TQ2G83CFR_48_config;
  299. }
  300. #endif