ppd_gpio.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2015 General Electric Company
  4. */
  5. #ifndef __PPD_GPIO_H_
  6. #define __PPD_GPIO_H_
  7. #include <asm/arch/iomux-mx53.h>
  8. #include <asm/gpio.h>
  9. static const iomux_v3_cfg_t ppd_pads[] = {
  10. /* FEC */
  11. MX53_PAD_EIM_A22__GPIO2_16,
  12. /* Video */
  13. MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */
  14. MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */
  15. MX53_PAD_CSI0_DAT10__GPIO5_28, /* DATA_WIDTH_CTRL */
  16. MX53_PAD_CSI0_PIXCLK__GPIO5_18, /* HOST_CONTROLLED_RESET_TO_LCD_N */
  17. MX53_PAD_EIM_DA2__GPIO3_2, /* LVDS1_MUX_CTRL */
  18. MX53_PAD_EIM_DA3__GPIO3_3, /* LVDS0_MUX_CTRL */
  19. MX53_PAD_EIM_A21__GPIO2_17, /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */
  20. MX53_PAD_CSI0_DAT11__GPIO5_29, /* BACKLIGHT_ENABLE */
  21. MX53_PAD_DISP0_DAT9__PWM2_PWMO, /* IMX535_PWM2_TO_LCD_CONNECTOR */
  22. /* I2C */
  23. MX53_PAD_EIM_A20__GPIO2_18, /* RESET_I2C1_BUS_SEGMENT_MUX_N */
  24. /* SPI */
  25. MX53_PAD_DISP0_DAT23__GPIO5_17,
  26. MX53_PAD_KEY_COL2__GPIO4_10,
  27. MX53_PAD_KEY_ROW2__GPIO4_11,
  28. MX53_PAD_KEY_COL3__GPIO4_12,
  29. MX53_PAD_PATA_DATA7__GPIO2_7, /* BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N */
  30. };
  31. struct gpio_cfg {
  32. unsigned int gpio;
  33. int value;
  34. };
  35. #define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16)
  36. #define UD_SCAN_CTRL IMX_GPIO_NR(5, 21)
  37. #define LR_SCAN_CTRL IMX_GPIO_NR(5, 20)
  38. #define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3)
  39. #define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2)
  40. #define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18)
  41. #define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28)
  42. #define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28)
  43. #define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29)
  44. #define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22)
  45. #define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27)
  46. #define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17)
  47. #define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18)
  48. #define ECSPI1_CS0 IMX_GPIO_NR(5, 17)
  49. #define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
  50. #define ECSPI1_CS2 IMX_GPIO_NR(4, 11)
  51. #define ECSPI1_CS3 IMX_GPIO_NR(4, 12)
  52. #define BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N IMX_GPIO_NR(2, 7)
  53. static const struct gpio_cfg ppd_gpios[] = {
  54. /* FEC */
  55. /* Drive Low as GPIO output for 25ms per Eth Phy IX spec */
  56. /* Then Drive High as GPIO output to bring Eth Phy IC out of reset */
  57. { RESET_IMX535_ETHERNET_PHY_N, 0 },
  58. { RESET_IMX535_ETHERNET_PHY_N, 1 },
  59. /* Video */
  60. { UD_SCAN_CTRL, 0 },
  61. { LR_SCAN_CTRL, 1 },
  62. #ifdef PROPRIETARY_CHANGES
  63. { LVDS0_MUX_CTRL, 1 },
  64. #else
  65. { LVDS0_MUX_CTRL, 0 },
  66. #endif
  67. { LVDS1_MUX_CTRL, 1 },
  68. { HOST_CONTROLLED_RESET_TO_LCD_N, 1 },
  69. { DATA_WIDTH_CTRL, 0 },
  70. { RESET_DP0_TRANSMITTER_N, 1 },
  71. { RESET_DP1_TRANSMITTER_N, 1 },
  72. { POWER_DOWN_LVDS0_DESERIALIZER_N, 1 },
  73. { POWER_DOWN_LVDS1_DESERIALIZER_N, 1 },
  74. { ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 },
  75. { RESET_I2C1_BUS_SEGMENT_MUX_N, 1 },
  76. { ECSPI1_CS0, 1 },
  77. { ECSPI1_CS1, 1 },
  78. { ECSPI1_CS2, 1 },
  79. { ECSPI1_CS3, 1 },
  80. { BUFFERED_HOST_CONTROLLED_RESET_TO_DOCKING_CONNECTOR_N, 1 },
  81. };
  82. #endif /* __PPD_GPIO_H_ */